how to use the design results of the vhdl code for a program in C code
in [FPGA]
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From: lolita grenoble on 15 Mar 2010 05:51 hello, i need help. i work over an algo in C langage that verifies a design described in VHDL for it, i want take all informations from my vhdl code for use them in my programme in C and i don't know how. |