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From: Gabor on 4 Nov 2009 15:44
On Nov 4, 2:51 pm, ed <ed.agu...(a)gmail.com> wrote:
> Just implemented the shift-register reset. Worked like a champ!
> Thanks :)
>
> But I still want to know why the state machine didn't start in its
> initial state after configuration....

A typical scenario is this:

1) Global Set & Reset is released at the end of configuration,
asynchronous to any clock in the design and with variable delay
throughout the device.

2) Your state machine is "released" from its initial state,
one bit of the state variable at a time. If your clock is
slow you might see the release of reset to all bits in the
same clock period MOST of the time.

3) If not all bits start up at once, your next state can be
different for different bits of the state variable. In the
case of a one-hot state machine, this can lead to a zero-hot
or multiple-hot state.

The effects of asynchronous start-up is magnified when the
the clock is at a higher speed and/or the state logic is
placed over a large area of the device.

Regards,
Gabor
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