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From: Robert Redelmeier on 10 Apr 2010 14:24 In alt.lang.asm Rod Pemberton <do_not_have(a)havenone.cmm> wrote in part: > "Robert Redelmeier" <redelm(a)ev1.net.invalid> wrote in message >> In alt.lang.asm Nathan Baker <nathancbaker(a)gmail.com> wrote in part: >> > There was a time when, every few years, the CPU clock speed >> > seemed to be increasing geometrically... >> > >> > 1 MHz > 8 MHz > 25 MHz > 90 MHz > 133 MHz > 500 MHz >> > >> > But when they got into the GHz range, the trend stopped. There is >> > no longer a "user noticable" increase in performance gained by >> > purchasing new hardware. This places the burden on software. >> >> Even outside of niches (video compression is still CPU-bound), this >> really is not true. The trend stopped mostly because it didn't pay. >> CPU time has dwindled to insignificance for common tasks, but other >> things (video rendering, disk seek, network response) have not. >> > Yes, the Amiga PC model, using a processor with multiple > coprocessors, was a brilliant advancement, wasn't it? > It's too bad PC's are still struggling to adopt the model... The original PC also had numerous support chips and a coprocessor 8087 , and Intel produced an 8089 IO coprocessor but I'm not aware of it being used. Intel shyed away from multiprocessing (IIRC) for many years from the iAPX/432 failure. > I was going to ask NB when multi-core x86 production started. > Wasn't it right were the clock speed doubling stops? i.e., > around 1GHz? More like 2-3 GHz, but your point remains good. Higher clocks are certainly possible on simpler cores (Pentium4) but that drops IPC. Simplifying somewhat, the real problem is local heat -- a shrink can run faster, speed increases linearly but the area available for heat removal decreases by the square. For many years, voltage could also drop with process shrinks so that reduced heat generation. But not much more which stalled clocks. So the additional xtors get used for multicore which spreads the heat out. Moore's Law gives you xtors but says nothing about speed. -- Robert
From: Maxim S. Shatskih on 11 Apr 2010 15:24 > More like 2-3 GHz, but your point remains good. Higher clocks are > certainly possible on simpler cores (Pentium4) but that drops IPC. P4 was the most complex core ever made, that's why it was discontinued and replaced with the desktop versions of Pentium-M (which was more-or-less advanced P-III Mobile) under the name "Core". -- Maxim S. Shatskih Windows DDK MVP maxim(a)storagecraft.com http://www.storagecraft.com
From: Robert Redelmeier on 11 Apr 2010 15:54 In alt.lang.asm Maxim S. Shatskih <maxim(a)storagecraft.com.no.spam> wrote in part: > P4 was the most complex core ever made, that's why it was discontinued > and replaced with the desktop versions of Pentium-M (which was > more-or-less advanced P-III Mobile) under the name "Core". Which itself is basically a tweaked PentiumPro. I grant you the P4 had lots of xtors for the deep pipelining, but as a dual-issue was not as complex as triple-issue CPUs (iPPro...iCore & K6...Phenom), at least from a clock-synch PoV. P4 died from the poor IPC. As a stopgap after Itanium cratered, I don't think it was expected to survive. -- Robert
From: Phil Carmody on 11 Apr 2010 18:11
Robert Redelmeier <redelm(a)ev1.net.invalid> writes: > In alt.lang.asm Maxim S. Shatskih <maxim(a)storagecraft.com.no.spam> wrote in part: >> P4 was the most complex core ever made, that's why it was discontinued >> and replaced with the desktop versions of Pentium-M (which was >> more-or-less advanced P-III Mobile) under the name "Core". > > Which itself is basically a tweaked PentiumPro. > > I grant you the P4 had lots of xtors for the deep pipelining, > but as a dual-issue was not as complex as triple-issue CPUs > (iPPro...iCore & K6...Phenom), at least from a clock-synch PoV. > > P4 died from the poor IPC. As a stopgap after Itanium cratered, > I don't think it was expected to survive. It was an experiment with more extreme architectural elements than its intel predecessors (pipeline depth, #ooo in flight, double-pumped ALUs), but seems to have suffered from some contradictory cost-cutting (ALUs being able to handle 4 IPC, but only 3 could be physically fed to them per tick, sub-par caches, etc.). I think they were hoping they could build on it, as it went through several revisions, but it only clicked later that it was a dead-end mess. All IIRC, which, given how long ago it was, is unlikely. Phil -- I find the easiest thing to do is to k/f myself and just troll away -- David Melville on r.a.s.f1 |