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From: Jk on 18 Mar 2010 09:46

Hi,

I'm working with the xilinx xapp1052 Bus Master DMA model. The data
received through DMA on the PCI-Express link is written to the fpga
Block RAM. I have added my design to this, which reads data from this
block ram and processes it.
A Read DMA transfer is configured with a TLP size & TLP count and then
the endpoint design waits to receive data from the host application.
Now my problem is that everything works fine in simulation. But in
actual hardware, the host application does not always send data in the
configuration set. For example I set the DMA configuration to be TLP's
with 23 double word payloads each, but what I receive at the endpoint
is TLP's with data payloads of 16 double words. This disturbs the rest
of the design which is expecting to receive data in a specific
format.Is that normal?

Jk
From: Charles Gardiner on 18 Mar 2010 10:02
Hi Jk,

if I understand you correctly you are performing a memory read from system memory?
In this case what you are observing is perfectly normal. It is called the read
completion boundary (RCB). The completer (here the root complex) can respond with
multiple completions to a single request. The spec says a root complex may
implement an RCB of 64 Byte (16 DW) or 128 Byte (32 DW). All other components
(bridge, switch, endpoint) may only implement an RCB of 128.

System software should set bit 3 in the Link Control register to indicate which
RCB option your root complex implements. I hope Xilinx makes this status signal
available to your hardware / state machines. I know Lattice does.

You have two options:
1) Never issue a request which crosses an RCB boundary (16DW or 32DW). This way
you will always get a single completion. You may well loose some bandwidth though.

2) Change your hardware to handle multiple completions. You are guaranteed these
arrive in order of increasing address.

Regards,
Charles

Jk schrieb:
> Hi,
>
> I'm working with the xilinx xapp1052 Bus Master DMA model. The data
> received through DMA on the PCI-Express link is written to the fpga
> Block RAM. I have added my design to this, which reads data from this
> block ram and processes it.
> A Read DMA transfer is configured with a TLP size & TLP count and then
> the endpoint design waits to receive data from the host application.
> Now my problem is that everything works fine in simulation. But in
> actual hardware, the host application does not always send data in the
> configuration set. For example I set the DMA configuration to be TLP's
> with 23 double word payloads each, but what I receive at the endpoint
> is TLP's with data payloads of 16 double words. This disturbs the rest
> of the design which is expecting to receive data in a specific
> format.Is that normal?
>
> Jk
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