CPLD Jitter
in [FPGA]
|
From: Andrew Holme on 29 Aug 2005 19:15 John_H wrote: > You're taking the bandwidth into account? Of course. I'm subtracting 10dB for 10Hz RBW. > You noted an improvement going from 100k to 500k comparison > frequencies. If power-supply noise were dominant, I wouldn't expect > to see that 13 dB change in phase noise. No, there was no difference, no 13dB change. That was my point.
From: Jim Granville on 29 Aug 2005 20:38 Andrew Holme wrote: > Thanks to all for the suggestions. <snip> > This gives 20nV/sqrt(Hz). Since U4 output is a 50% duty cycle square > wave(XOR PFD), presumably I would still only need 40nV/sqrt(Hz) on the > regulator output? Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05 with 100n > + 10n hanging off its output? Once you have cleaner supply filtering to the 1G125, you could try different Phase comparitors : eg a HC4046/7046, then try the same logic inside the CPLD. Gives you ideas, and also a comparison point. Simple XOR detectors have poor PSRR, as you note, and also low phase gain. Better synthesisers use charge balancing, or a combination of detectors / gains. Good designs also avoid a complete null, on phase match, to avoid dead-zones, on their charge balancing detectors. If you are looking for absolute best performance, also look at doing a balanced (Push-Pull) Phase Det - that gives better PSR. -jg
From: Joerg on 29 Aug 2005 20:40 Hello Andrew, > Yesterday, I thought the phase noise might be due to the reference or the > PFD, and when I estimated the dBc/Hz at the PFD, I thought the numbers were > poor. Now, I'm not so sure the CPLD is the biggest problem. I think I may > just need better power supply filtering after the monolithic regulators. So just hang the analyzer onto the VCC and look. But ease it onto the rail slowly and don't power cycle the board while probing. Else you might fry its input. Regards, Joerg http://www.analogconsultants.com
From: Mike on 29 Aug 2005 23:26 "Andrew Holme" <andrew(a)nospam.com> wrote in message news:desmbt$i07$1$8302bc10(a)news.demon.co.uk... > The dividers and the phase detector of my experimental frequency > synthesizer > are implemented in a 15ns Altera MAX7000S CPLD. I've tried different > multiplication factors (kN) to see how the close-in phase noise varies. > At > a 1 KHz offset, I get: > > -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz) > -95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz) > > Calculating the equivalent phase noise at the PFD: > > -82-20*log10(198) = -128 dBc/Hz > -95-20*log10(39) = -127 dBc/Hz > > Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect > these > to differ by 13 dB if the noise was mainly due to a fixed amount of time > jitter at the PFD. > > I'm using a 10 MHz canned crystal oscillator, which I'm dividing down > (inside the CPLD) to obtain the reference frequencies. I've read these > are > good for at least -130 dBc/Hz (before dividing down) so I'm a bit > dissappointed with my noise levels. Maybe it got a bit too hot when I > soldered it to the ground plane! I must try another.... > > Googling for "altera cpld jitter" doesn't turn-up much, and they don't > mention jitter in the datasheet. Does anyone know what sort of > performance > can be expected from a CPLD in this regard? I don't know if the CPLD, or > my > circuit lash-up is the root cause. > > A full write-up of the project can be found at > http://www.holmea.demon.co.uk/Frac2/Main.htm It has a fractional-N > capability, but noise-levels are the same in integer-N mode with the > external RAM disabled. I'm not sure why you think you should be seeing a 13dB difference at the input. If I can make some gross assumptions here, I'm going to assume that your system is second order, highly overdamped (the poles are widely separated), and that the bandwidth, even at the 100kHz update rate, is much greater than 1kHz. Then, if your dominant noise source is at the reference input, the gain from input to output close to the carrier is N. If your dominant noise source is at the VCO input, the gain close to the carrier is N/(Kd*R). In both cases, you have a gain of N. Looking at your data, I see that if the noise at 1KHz offset is constant, whether it's at the reference input or the VCO input, the noise should change by about 14dB. You're measuring 13dB instead of 14dB... so, what's the problem? -- Mike --
From: Mike on 30 Aug 2005 10:55 "Mike" <mike(a)nospam.com> wrote in message news:MlQQe.1853$mH.1380(a)fed1read07... > "Andrew Holme" <andrew(a)nospam.com> wrote in message > news:desmbt$i07$1$8302bc10(a)news.demon.co.uk... >> The dividers and the phase detector of my experimental frequency >> synthesizer >> are implemented in a 15ns Altera MAX7000S CPLD. I've tried different >> multiplication factors (kN) to see how the close-in phase noise varies. >> At >> a 1 KHz offset, I get: >> >> -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz) >> -95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz) >> >> Calculating the equivalent phase noise at the PFD: >> >> -82-20*log10(198) = -128 dBc/Hz >> -95-20*log10(39) = -127 dBc/Hz >> >> Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect >> these >> to differ by 13 dB if the noise was mainly due to a fixed amount of time >> jitter at the PFD. >> >> I'm using a 10 MHz canned crystal oscillator, which I'm dividing down >> (inside the CPLD) to obtain the reference frequencies. I've read these >> are >> good for at least -130 dBc/Hz (before dividing down) so I'm a bit >> dissappointed with my noise levels. Maybe it got a bit too hot when I >> soldered it to the ground plane! I must try another.... >> >> Googling for "altera cpld jitter" doesn't turn-up much, and they don't >> mention jitter in the datasheet. Does anyone know what sort of >> performance >> can be expected from a CPLD in this regard? I don't know if the CPLD, or >> my >> circuit lash-up is the root cause. >> >> A full write-up of the project can be found at >> http://www.holmea.demon.co.uk/Frac2/Main.htm It has a fractional-N >> capability, but noise-levels are the same in integer-N mode with the >> external RAM disabled. > > I'm not sure why you think you should be seeing a 13dB difference at the > input. If I can make some gross assumptions here, I'm going to assume that > your system is second order, highly overdamped (the poles are widely > separated), and that the bandwidth, even at the 100kHz update rate, is > much greater than 1kHz. Then, if your dominant noise source is at the > reference input, the gain from input to output close to the carrier is N. > If your dominant noise source is at the VCO input, the gain close to the > carrier is N/(Kd*R). In both cases, you have a gain of N. Looking at your > data, I see that if the noise at 1KHz offset is constant, whether it's at > the reference input or the VCO input, the noise should change by about > 14dB. > > You're measuring 13dB instead of 14dB... so, what's the problem? I think we can take things one step further. Mini Circuits thoughtfully provides us with the typical phase noise of their VCO (-86dBc @1kHz offset), and the VCO gain (1-4MHz/V, which we will take to be 2.5MHz/V). If we insert this noise at the VCO output in a simple PLL, and again assuming that you're overdamped with a loop bandwidth wider than 1kHz, the loop gain at 1kHz offset is approximately wN/(KoKdR). So, based on your measured values, -95 = -86 + 20log(wM/(KoKdR)) where w = 2pi*1kHz Ko = 2pi*2.5MHz M = 39 Solving for KdR, KdR = wM/(Ko*10^(-9/20)) = 0.044 You haven't published your loop filter design, but most of the PLLs I've designed in the past few years have had Kd*R somewhere in the range of 0.01 to 0.05, so the value I've obtained above looks like it might be about right. The point of all this is that your noise is probably not coming from your crystal reference oscillator. I think it's more likely that it's coming from your VCO, and (if my assumptions about Kd*R are roughly correct) is approximately what you'd expect to see. -- Mike --
First
|
Prev
|
Next
|
Last
Pages: 1 2 3 4 5 Prev: Evolutionary VHDL code example Next: modelsim simulation problem |