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From: quark.flavour on 6 Jan 2008 04:16

> I ported the open source Lattice Mico32 CPU to Xilinx and Altera
> chips -- Comparable
> to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's
> cross vendor RTL code
> and complete open source [1].

Sounds great! I've downloaded everything, the SoC, the wb-ddr
controller
and the simple ddr controller as well.

> Works fine with the wb_ddr controller on the said boards and powers
> for example
> http://www.youtube.com/watch?v=4MGKhFIujM4

Cool app!

> It's not the first complete open source SoC, and won't be the last one
> -- But it's a capable
> small footprint SoC plattform baeed on the wishbone interconnect. The
> only thing I'm
> currently really missing is a MMU.

You have the controller, is the MMU hard to code?

Andrew
From: jb on 6 Jan 2008 07:59
On Jan 6, 10:16 am, quark.flav...(a)gmail.com wrote:

> > I ported the open source Lattice Mico32 CPU to Xilinx and Altera
> > chips -- Comparable to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's
> > cross vendor RTL code and complete open source [1].
>
> Sounds great! I've downloaded everything, the SoC, the wb-ddr
> controller and the simple ddr controller as well.

I'd be happy if this could become a friendly cross vendor SoC
evironment, so please let me know if you're running into
difficulties.I understand that the absence of any documentation
for the build environment is a major hurdle :(

Hearing about success stories would be nice too :)

> > It's not the first complete open source SoC, and won't be the last one
> > -- But it's a capable small footprint SoC plattform baeed on the
> > wishbone interconnect. The only thing I'm currently really missing is
> > a MMU.
>
> You have the controller, is the MMU hard to code?

I'm currently evaluating how to proceed -- I think a soft loaded TLB
architecture is the way to go. But I need to understand precisely how
the caches work inside the LM32...

jb
From: posedge52 on 6 Jan 2008 08:34
On Jan 5, 2:52 pm, j...(a)capsec.org wrote:
> On Jan 5, 12:31 pm, posedg...(a)yahoo.com wrote:
>
> > I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
> > -6T F).
> > Is there any *simple* demo that stores a picture bitmap in the builtin
> > DDR SDRAM and sends the bitmap to the VGA port continously ..?
>
> I designed a DDR controller with wishbone interface for that board --
> I know it works well
> on a bunch of S3E-500 StarterKits, one S3E-1600 and I even use a
> variant on the XUPV2P
> Board.
>
> But it's not ideally suited for your design, because it uses 2
> BlockRAMs to cache access to the
> DRAM -- If you can live with that....
>
> Seehttps://roulette.das-labor.org/bzrtrac/wiki/wb_ddr

I downloaded and tried it. And it seems to work. At least data_ok and
data_ok_lt shines.
I just had to write a script to download from your Trac system and
rename 'DCM_SP' to DCM.
Now I'm trying to reverse engineer fml_memtest() so I can use it for
other things.
Is your code BSD licensed? (like NetBSD)
From: quark.flavour on 7 Jan 2008 07:37
On Jan 6, 1:59 pm, j...(a)capsec.org wrote:
> I'd be happy if this could become a friendly cross vendor SoC
> evironment, so please let me know if you're running into
> difficulties.I understand that the absence of any documentation
> for the build environment is a major hurdle :(

Of course, I've tried to load the firmware and it runs smoothly
except for a long term error (ld0) that, as far as I've seen, occurrs
in the first few 5 - 8 read/write operations. I still have to dig into
the
problem, if I'll find something I'll report to you immediately. Maybe
it's
something about the DCM, a difference between the boards.
BTW the absence of documentation is not a problem at all since
I'm working on memory interface and your code is very good
and readable.

> Hearing about success stories would be nice too :)

Well, I'll do my best but I'm just learning, and I cannot say I've
ever done
something worthy as far, just experiments!

> I'm currently evaluating how to proceed -- I think a soft loaded TLB
> architecture is the way to go. But I need to understand precisely how
> the caches work inside the LM32...

Keep up the good work, I'll keep an eye on the progress of the
project.

Andrew
From: jb on 8 Jan 2008 06:53
Hi,

> I downloaded and tried it. And it seems to work. At least data_ok and
> data_ok_lt shines.

Good -- "*_lt" is the longterm variant which, once lit, is never
reset.
If "error_lt" does *not* lite up, everything is fine.

> I just had to write a script to download from your Trac system and
> rename 'DCM_SP' to DCM.

Strange, I remember DCM_SP is the DCM variant one should use in
Spartan3E... Can't remember for sure...

> Now I'm trying to reverse engineer fml_memtest() so I can use it for
> other things.

> Is your code BSD licensed? (like NetBSD)

I hereby place it under LGPL and will update the source code
accordingly soon.

I currently do not have the time to dig deeply into the HDL open
source
licensing issue -- but LGPL seems to fit the bill: you may use the
component wherever you like, without beeing forced to publish any
of your application...
But if you enhance the component itself, you're forced to "give back".


j.
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