Does Xilinx sync FIFO use dual port memory? Does this affect resource?
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From: dlopez on 3 Dec 2009 12:17 Hi, When using a synchronous FIFO, it seems like one can read and write into the FIFO at the same time. Does this means that the underlying memory is a Dual-Port blockram? If so, what is the cost of using such a dual port memory in a Xilinx FPGA. My experience is with ASIC, where most dual-port memory are about twice as big as their single-port counterpart. If the application permits the use a single port memory with a bit of logic avoiding the collision, it's definitely the way to go. However, if the Xilinx block ram are dual port 'for free', it's much easier to use the direct sync. FIFO... My application uses very fast burst writes, and continuous slow read. I could definitely use a normal single-port ram and make sure the burst-writes do not collide with the read. I just wonder if it's worth doing... Thanks! Diego --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Peter Alfke on 3 Dec 2009 12:32 On Dec 3, 9:17 am, "dlopez" <d...(a)designgame.ca> wrote: > Hi, > When using a synchronous FIFO, it seems like one can read and write into > the FIFO at the same time. > > Does this means that the underlying memory is a Dual-Port blockram? > All Xilinx (Spartan or Virtex) BlockRAMs are dual-ported "for free", and for a FIFO application you therefore always use one port to write, the other one to read. Each port has its own controls, including clock and clock enable and write enable. The two ports can use independent clocks, but in that case, the generation of FULL and Empty is more complex, since these signals are being activated in one clock domain, and deactivated in the opposite one. That's what makes the design of high-performance asynchronous FIFOs so challenging. Peter Alfke, FIFO designer since 1970.
From: austin on 3 Dec 2009 13:02 Diego, The Xilinx FPGA device has made all the choices for you, so it really doesn't matter how much area the BRAM takes, the real question is: "is the device I have chosen adequate to solve my problem?" Making a device with a single port memory for a FIFO might be more efficient in an ASIC, but in a FPGA device, it is best to build the most capable possible structures, in order to address the largest possible market. "FPGA thinking" is completely different from "ASIC thinking" in terms of efficiency, costs, areas. Not better, not worse, just different. Austin
From: maxascent on 3 Dec 2009 14:29 You can also use the distributed RAM to create a memory rather than the block RAMs. These are more resource efficient if you dont need large memories or some of the features of the block RAM like true dual port. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
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