NASM 0.98.39 vs. NASM 2.03.01 disassembly
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From: NathanCBaker on 9 Sep 2008 01:29 On Sep 9, 12:04 am, Chuck Crayne <ccra...(a)crayne.org> wrote: > > http://en.wikipedia.org/wiki/NCR_Century_100 > I bet you're thinking that this thread gives "Dancing Rod" a new meaning? :) Could I trouble you for an instruction list (w/opcodes)? I found this: http://www.thecorememory.com/index.html but perhaps I am using the wrong Google search terms. Nathan.
From: Frank Kotler on 9 Sep 2008 01:34 Rod Pemberton wrote: .... > Then it would be crud eax, eax, 0, 2 and still need to produce a movzx eax, > ax. > > But, either way, how does one easily, without a large macro, get "ax" when > given "eax" etc.? AFAIK, there is no register size conversion feature in > NASM. I suppose it depends on how you define "large"... I think you're right that Nasm doesn't have any pretty "built in" way to do it... %macro crud 1 %ifidni %1, eax %define %%reg16 ax %elifidni %1, ebx %define %%reg16 bx %elifidni %1, ecx %define %%reg16 cx %elifidni %1, edx %define %%reg16 dx %elifidni %1, esi %define %%reg16 si %elifidni %1, edi %define %%reg16 di %elifidni %1, ebp %define %%reg16 bp %else %error "Parameter must be a 32-bit GP register." %endif movzx %1, %%reg16 %endm bits 32 crud eax ;----------------------- I wasn't sure what you were doing with those other parameters, so I ignored 'em. :) The "0" select between movzx and movsx? The "2" select between al and ax? If so, yeah that would make for a larger macro, as would expanding it to 64-bit registers. I guess you could call that "large". Not very "elegant", IMO. What would you "like" Nasm to let you do? Best, Frank
From: NathanCBaker on 9 Sep 2008 15:51 On Sep 9, 1:29 am, NathanCBa...(a)gmail.com wrote: > > Could I trouble you for an instruction list (w/opcodes)? > > I found this:http://www.thecorememory.com/index.html > but perhaps I am using the wrong Google search terms. > I am not sure if I am getting "warmer" or getting "colder" but my digging points me in the direction of the NEAT/3 language. A Google on -that- informs me that some dude by the name of Randall Hyde (anybody know him?) cites it in a piece about the history of High Level Assemblers: http://webster.cs.ucr.edu/AsmTools/HLA/HLADoc/HLARef2_html/HLARef.html ,--- 2 What is a "High Level Assembler"? .... David Salomon describes several different high level assemblers in his text. The examples he describes are PL/360, NEAT/3, PL516, and BABBAGE. .... The NEAT/3 language is a much lower-level language; basically it is an assembly language for the NCR Century computers that provide COBOL- style data declarations. Most of its "instructions" translate one-for- one into Century machine instructions, though it does automatically insert code to convert data types from one format two another if the data types of an instructions operands are incompatible. `--- Hmm... converting data types "on the fly" so to speak. Smacks of "dynamic typing" to me. Wouldn't that make NEAT/3 "higher level" than HLA?? IIRC, a certain someone in this NG once accused Randy of "having his head in the high-level language world." :) Well, I think the snake just bit me: http://bitsavers.org/pdf/ncr/century/ Nathan.
From: Rod Pemberton on 9 Sep 2008 17:33 "Frank Kotler" <fbkotler(a)verizon.net> wrote in message news:ga51u8$bga$1(a)aioe.org... > The "0" select between movzx and movsx? The "2" select between al and > ax? If so, yeah that would make for a larger macro, as would expanding > it to 64-bit registers. I guess you could call that "large". Not very > "elegant", IMO. It was a made up example... :) The issue originally came up with SETcc (and MOVZX), not LAR/LSL. My code was using only 32-bit registers, but at the time I needed an instruction which doesn't exist: SETcc r32. But, x86 has SETcc r8. I needed to produce a _completely_ orthogonal (all 8 GPs) SETcc but unfortunately SETcc required use of 8-bit sub-registers. Also, while there are 8 8-bit registers, each of the 8 32-bit registers don't have an 8-bit sub-register. %macro setcc 2 ;%1 is condition code and %2 is register .... %endmacro This is simple for eax, ebx, ecx, edx, but requires four sections: %ifidn %2,eax set%+1 al movzx %2,al ; for 32-bit code... e.g., setcc r32 %elifidn ... ; 3 more sections with similar code for ebx, ecx, edx %endif It's not so simple to make SETcc orthogonal for for esi, edi, ebp, esp, especially since they don't have an 8-bit sub-register: %ifidn %2,esi push eax %elifidn ...; 3 more sections with similar code for edi, ebp, esp %endif %ifidn %2,eax ....;code for eax, ebx, ecx, edx like that above %else ; main code for edi, esi, ebp, esp set%+1 al movzx %2,al %endif %ifidn %2,esi pop eax %elifidn...; 3 more sections with similar code for edi, ebp, esp %endif After expanding all that you'll end up with a 40 lines of code... The thought that came up for me was: "Why can't I simply pass eax, ebx, ecx, edx, ebp, esp, esi, edi to some function and get an appropriate register for SETcc and MOVZX? Why doesn't NASM support something more like this:" %macro setcc 2 ;%1 is condition code and %2 is register %ifishighreg %2 push exx(xl(%2)) %endif set%+1 xl(%2) movzx %2, xl(%2) %ifishighreg %2 pop exx(xl(%2)) %endif %endif 1) Where %ifishighreg is true for esi, edi, esp, ebp. 2) Where xl() is passed eax and returns al, ebx .. bl, ecx .. cl, edx .. dl, and returns al for esi, edi, ebp, esp. 3) Where exx() is passed one of 4 lower 8-bit registers (al, bl, cl, dl) and returns eax, ebx, ecx, edx, respectively. Maybe I didn't read the 0.98.39 manual well enough, maybe I need to read the 2.03.01 manual, and maybe this is just based on my desire to code C... Rod Pemberton
From: Rod Pemberton on 9 Sep 2008 18:22
"Chuck Crayne" <ccrayne(a)crayne.org> wrote in message news:20080908210441.1315bf05(a)thor.crayne.org... > On Mon, 8 Sep 2008 17:57:26 -0400 > "Rod Pemberton" <do_not_have(a)nohavenot.cmm> wrote: > > http://en.wikipedia.org/wiki/NCR_Century_100 > > The article doesn't mention my name, but I was responsible for > designing that part of the cpu logic which dealt with instruction > decoding and execution. Seiji Morimoto designed the I/O interface > logic. Fair enough. It's editable. Although given the very early timeframe of your expertise, I do have to wonder how closely your understanding of the early technology matches that of post-1975 microprocessors. I spent nearly every moment of my free time for almost a decade prior to university learning everything I could about electronics, circuit design, schematics, programming, and microprocessors. I was reading schematics by about age 15 and had a collection of them for the popular computers at the time. I put 3 1/2 years on an 4 yr. EE degree before becoming bored and having to deal with life circumstances. I also spent about five years of my life as an electronic technician tracking down and fixing problems with DSPs and analog audio circuitry. While I might not be an "expert" in cpu design from your perspective, I think my understanding is about as well developed as one can expect for someone not in circuit design, and far above that of the common programmer. Rod Pemberton |