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From: =?ISO-8859-1?Q?Niels_J=F8rgen_Kruse?= on 10 Oct 2006 16:04
An EEtimes article
<http://www.eetimes.com/showArticle.jhtml?articleID=193105767>,
has the following information, not previously public (AFAIK):

1) L2 cache is 8 MB total (for the die presumably)

2) Memory bandwidth is 75Gbyte/second (for the die)

3) Minimum voltage for full operation (doing work) is 0.8V (for some
significant bin presumably).

--
Mvh./Regards, Niels J?rgen Kruse, Vanl?se, Denmark
From: ranjit_mathews@yahoo.com on 12 Oct 2006 05:17
Niels Jørgen Kruse wrote:
> An EEtimes article
> <http://www.eetimes.com/showArticle.jhtml?articleID=193105767>,
> has the following information, not previously public (AFAIK):
>
> 1) L2 cache is 8 MB total (for the die presumably)

That's what it was on the high end NorthStar Power3 based servers
nearly a decade back, although not on die.

> 2) Memory bandwidth is 75Gbyte/second (for the die)
>
> 3) Minimum voltage for full operation (doing work) is 0.8V (for some
> significant bin presumably).
>
> --
> Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark

From: =?ISO-8859-1?Q?Niels_J=F8rgen_Kruse?= on 12 Oct 2006 16:38
ranjit_mathews(a)yahoo.com <ranjit_mathews(a)yahoo.com> wrote:

> Niels J?rgen Kruse wrote:
> > An EEtimes article
> > <http://www.eetimes.com/showArticle.jhtml?articleID=193105767>,
> > has the following information, not previously public (AFAIK):
> >
> > 1) L2 cache is 8 MB total (for the die presumably)
>
> That's what it was on the high end NorthStar Power3 based servers
> nearly a decade back, although not on die.

Northstar != POWER3. The POWER6 has 32 MB of offdie cache too
(80GB/second bandwidth). Since the amount is a reduction from POWER5 and
IBM has discontinued their eDRAM in 65 nm, I guess this must be SRAM.

A lot of slides from the Microprocessor Forum can be seen at
<http://www.tecchannel.de/news/themen/technologie/450386/>. Those who
can read german can get something out of the text too :-)

It was a surprise to see the dispatch bandwidth increased to 7
instructions per clock (from 5 in the POWER5). It was a common
expectation that POWER6 had to be narrower to achieve the high clock.

--
Mvh./Regards, Niels J?rgen Kruse, Vanl?se, Denmark
From: Del Cecchi on 12 Oct 2006 16:55
Niels J?rgen Kruse wrote:
> ranjit_mathews(a)yahoo.com <ranjit_mathews(a)yahoo.com> wrote:
>
>
>>Niels J?rgen Kruse wrote:
>>
>>>An EEtimes article
>>><http://www.eetimes.com/showArticle.jhtml?articleID=193105767>,
>>>has the following information, not previously public (AFAIK):
>>>
>>>1) L2 cache is 8 MB total (for the die presumably)
>>
>>That's what it was on the high end NorthStar Power3 based servers
>>nearly a decade back, although not on die.
>
>
> Northstar != POWER3. The POWER6 has 32 MB of offdie cache too
> (80GB/second bandwidth). Since the amount is a reduction from POWER5 and
> IBM has discontinued their eDRAM in 65 nm, I guess this must be SRAM.

eDRAM still appears to be available in 65nm bulk (CU65HP), don't know
about in SOI
>
> A lot of slides from the Microprocessor Forum can be seen at
> <http://www.tecchannel.de/news/themen/technologie/450386/>. Those who
> can read german can get something out of the text too :-)
>
> It was a surprise to see the dispatch bandwidth increased to 7
> instructions per clock (from 5 in the POWER5). It was a common
> expectation that POWER6 had to be narrower to achieve the high clock.
>


--
Del Cecchi
"This post is my own and doesn?t necessarily represent IBM?s positions,
strategies or opinions.?
From: =?ISO-8859-1?Q?Niels_J=F8rgen_Kruse?= on 12 Oct 2006 17:34
Del Cecchi <cecchinospam(a)us.ibm.com> wrote:

> Niels J?rgen Kruse wrote:
> > Northstar != POWER3. The POWER6 has 32 MB of offdie cache too
> > (80GB/second bandwidth). Since the amount is a reduction from POWER5 and
> > IBM has discontinued their eDRAM in 65 nm, I guess this must be SRAM.
>
> eDRAM still appears to be available in 65nm bulk (CU65HP), don't know
> about in SOI

OK, I don't remember exactly where I got that notion. 32MB SRAM is
certainly possible in 65nm though.

--
Mvh./Regards, Niels J?rgen Kruse, Vanl?se, Denmark
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