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From: Test01 on 20 Feb 2010 21:51
I have a question about Altera Stratix4GX PCIe Hard IP root port
question. As per my understanding, the back end of the root-port
supports Avalon ST Bus thorugh which I can feed TLPs to pass
transactions downstream using the Hard IP root port. Is it possible
to put it in a mode where all the transactions are passed on
downstream - even the PCI conig cycles?
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