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From: KJ on 1 May 2010 15:45
On May 1, 10:47 am, "maxascent"
<maxascent(a)n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> I am using an asynchronous fifo to cross the two clock domains so I would
> think that as long as I respect the fifo flags on each side then crossing
> from one domain to the next should not be a problem.

Only those signals that cross the clock domain that you are absolutely
sure are done correctly should be flagged as being multi-cycle...So
that might be the data and control signals for the fifo, not
everything that crosses from one domain to the other.

> So I
> would think that I need to tell ISE to ignore the paths between each domain

And what if you inadvertantly have some clock domain crossnig that is
not done correctly? Now timing analysis won't flag that for
you...it's also far too easy to convince yourself that you've done
things correctly...only to find out later that you were wrong.

Kevin Jennings
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