Synplify constraint problem
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From: maxascent on 30 Apr 2010 11:16 I have a design in a Virtex 5 with an asynchronous fifo that has a write clock of 100 MHz and a read clock of 300 MHz. Both clocks are driven from a PLL. I want to tell Synplify that the two clocks can be in different clock groups for timing and so have a false path between them. However Synplify just looks at the input clock on the PLL and then auto defines the other two clocks and puts them in the same clock group. Any ideas how I seperate them into two groups? Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.com
From: Amal on 30 Apr 2010 20:34 On Apr 30, 11:16 am, "maxascent" <maxascent(a)n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I have a design in a Virtex 5 with an asynchronous fifo that has a write > clock of 100 MHz and a read clock of 300 MHz. Both clocks are driven from a > PLL. I want to tell Synplify that the two clocks can be in different clock > groups for timing and so have a false path between them. However Synplify > just looks at the input clock on the PLL and then auto defines the other > two clocks and puts them in the same clock group. Any ideas how I seperate > them into two groups? > > Thanks > > Jon > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com You can add constraints on the output of PLL and put them in different clock groups. This would automatically create a false path between the clocks. -- Amal
From: maxascent on 1 May 2010 04:05 >You can add constraints on the output of PLL and put them in different >clock groups. This would automatically create a false path between >the clocks. > >-- Amal I could declare each clock and put it in a different group but Synplify just ignores them as it finds the clocks by looking at the PLL and sets them in the same clock group. I need some way to overide this and create two different clock groups. Jon --------------------------------------- Posted through http://www.FPGARelated.com
From: KJ on 1 May 2010 09:57 On Apr 30, 11:16 am, "maxascent" <maxascent(a)n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > Both clocks are driven from a > PLL. I want to tell Synplify that the two clocks can be in different clock > groups for timing and so have a false path between them. Not to be a noodge, but declaring paths between two clock domains to be 'false paths' is not the proper approach. By *declaring* them to be false paths, you're allowing any crazy logic that connects the two clock domains to be acceptable for timing analysis...which it most certainly is not. You should be - Finding each and every clock domain crossing (the timing analyzer will find them) - Verifying that the logic connecting the two domains is appropriate handshaked - Individually specify that each identified logic path is multi- cycle. Wildcarding should be kept to a minimum, like only for collectively identifying the bits of a bus If you wildcard at a higher level you run the risk that some future (or current) design change will fit the wildcard spec and thus not get analyzed, but not be appropriate clock domain crossing logic so in reality the design will fail. Declaring all paths between clock domains to be false paths as you said you'd like to do is exactly the same as wildcarding everything and is a mistake waiting to come and bite you. Kevin Jennings
From: maxascent on 1 May 2010 10:47
I am using an asynchronous fifo to cross the two clock domains so I would think that as long as I respect the fifo flags on each side then crossing from one domain to the next should not be a problem. At the moment because the clocks from the pll are related ISE is trying to analyise the paths between them but is failing to meet the very small period of 1ns. So I would think that I need to tell ISE to ignore the paths between each domain otherwise the design will never P&R. Jon --------------------------------------- Posted through http://www.FPGARelated.com |