From: Dek on 22 Feb 2010 06:37
I'm working on a Virtex5 xc5vlx50 and in my design I need to use some
block ram. I generated the core with core generator, but when I
implement the design I got this warning during mapping:
WARNING:Pack:231 - trimming timing constraints from pin hit2/RAM1/BU2/
UE_DP.SINGLE_PRIM36.TDP of frag REGCLKBL connected to power/ground net
Does anyone knows what it mean and how can i fix it? I found nothing
neither on the xilinx site nor on the web
From: austin on 22 Feb 2010 10:45
It is a warning: you do not necessarily have to fix it.
The tools are telling you that a net to a constant (1=power, or
0=ground) had its timing constraint removed (ignored).
That is a perfectly OK thing to do.
It is up to you to read each warning, and check out what it means.
This one is easy, let it go.
From: Dek on 23 Feb 2010 09:20
On 22 Feb, 16:45, austin <aus...(a)xilinx.com> wrote:
> It is a warning: you do not necessarily have to fix it.
> The tools are telling you that a net to a constant (1=power, or
> 0=ground) had its timing constraint removed (ignored).
> That is a perfectly OK thing to do.
> It is up to you to read each warning, and check out what it means.
> This one is easy, let it go.
Thanks for the reply; the point is that I have a project that uses
some block ram; In functional simulation everything works fine, when I
do synthesys and place and route I got no errors, no timing related
problems, and just 2 kind of warnings:
Xst:2211: ... line 130: Instantiating black box module <ram_128>
( see http://groups.google.it/group/comp.lang.vhdl/browse_thread/thread/cf702b52f28c2674/702ad29181e18171#702ad29181e18171
Pack:231 - trimming timing constraints from pin as described above
If I try to do a post layout simulation of this design with Modelsim;
I got this warning:
# ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.195 ns; Observed := 0.006 ns; At : 191.527 ns
# Time: 191527 ps Iteration: 1 Instance: /newdaedalus_tb/top/
and the design does not behave like in functional analysis. I also
implemented the bitfile on real hardware but it doesn't work. That's
why I was asking about that warning, because I really can't get where
the problem could be...
I'm using the block ram @ 40 MHz, but it shouldn't be a problem,
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