From: whygee on
hi,

recently I read a quote about VHDL vs Verilog,
along the lines of "VHDL is made by SW people who
don't understand HW and vice versa"...

Does anybody know the exact wording and origin ?

yg
--
http://ygdes.com / http://yasep.org
From: rickman on
On Feb 12, 7:15 pm, whygee <y...(a)yg.yg> wrote:
> hi,
>
> recently I read a quote about VHDL vs Verilog,
> along the lines of "VHDL is made by SW people who
> don't understand HW and vice versa"...
>
> Does anybody know the exact wording and origin ?
>
> yg
> --http://ygdes.com/http://yasep.org

Just ignore the troll. I'd like to get an answer to your question.

Rick
From: KJ on
On Feb 12, 8:16 pm, Symon <symon_bre...(a)hotmail.com> wrote:

> ...to comp.lang.vhdl where you will find polite software people. Ask for
> Jonathan, Mike and KJ. Tell them I sent you.
>

Ooooo...you read my posts and am on your recommended reading list
now!!!

KJ
From: whygee on
KJ wrote:
> On Feb 12, 8:16 pm, Symon <symon_bre...(a)hotmail.com> wrote:
>> ...to comp.lang.vhdl where you will find polite software people. Ask for
>> Jonathan, Mike and KJ. Tell them I sent you.
> Ooooo...you read my posts and am on your recommended reading list now!!!

I did not know that I would trigger so many strong reactions,
you know, it's just a reference check for a paper,
I have no intention to start a vi vs emacs^W^W^Wnother
pointless flamewar.

regards,

> KJ
yg

--
http://ygdes.com / http://yasep.org
From: Petter Gustad on
whygee <yg(a)yg.yg> writes:

> Does anybody know the exact wording and origin ?

You mean this?

http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4

Petter
--
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