From: John Larkin on 3 Jul 2010 11:10
On Wed, 30 Jun 2010 18:50:42 -0700 (PDT), Bryan
>I work for Avnet, which seems not to be too popular with this crowd,
>but I will share my experience anyway. I have a project with
>XC6SLX16-2CSG324 and LPDDR that seems to work well with MIG 3.3 in ISE
>11.4. Granted, we are only running at 200 MHz. We do not provide a
>200 MHz input to the chip. We have a 66 MHz oscillator input to the
>FPGA. It is true that by default, MIG generates a design that assumes
>the native system clock is the same as the memory clock. The only
>clocking customization that MIG allows is the choice between single-
>ended or differential clock. However, since MIG provides all the HDL
>sources for the clock infrastructure, it is possible to modify the
>clocking structure to generate the correct memory clock given any
>system clock that meets the specifications of the PLL.
>I have some instructions that explains step-by-step how to do this for
>the Avnet board (www.em.avnet.com/spartan6lx-evl). If you are
>interested, please contact Avnet Technical Support (www.em.avnet.com/
>techsupport). In addition to this LPDDR example, Xilinx provides
>working hardware examples for DDR2 on the SP601 and DDR3 on the
>SP605. Avnet has another board with DDR3 that has been proven out at
>800 Mbps in hardware (www.em.avnet.com/spartan6lx150t-dev).
>The other critical thing to do with these DDR designs is proper PCB
>layout and termination, without which the design will fail. Xilinx
>provides some very specific layout guidelines in UG388 that need to be
>followed if you want the full memory interface performance.
>Xilinx recently published revised specifications for the MCB. See
>The Spartan-6 Memory Controller Block (MCB) has new data rate
>specifications and performance modes for DDR2 and DDR3 interfaces as
>specified in version 1.5 of the Spartan-6 FPGA Data Sheet (DS162):
>You should also be aware of the MIG Design Advisory Answer Record.
We (I work with Rob) have contacted our tech support guy at Avnet, and
asked him for your doc. After about six interchanges, we still can't
get our hands on it.
From: Bryan on 6 Jul 2010 00:02
Thanks for your patience. I have been in contact with your FAE, and
he now has the document. If he hasn't gotten it to you within a day
or two, please let me know.
From: John Larkin on 7 Jul 2010 18:47
On Mon, 5 Jul 2010 21:02:15 -0700 (PDT), Bryan
>Thanks for your patience. I have been in contact with your FAE, and
>he now has the document. If he hasn't gotten it to you within a day
>or two, please let me know.
Got it, thanks.
It's looking like V12.1 of the Xilinx software is much friendlier to
Spartan6's than 11 was. Things compile bigger, but seem to be closer
We just redesigned a block of 32 8-pole 48-bit-wide IIR digital
lowpass filters, from 6500 LUTs down to about 280, so they will
compile under 12.1.
Maybe 12.1 (or 12.2) and your procedure will fix our DRAM problems.