From: JimLewis on
On Apr 22, 5:41 pm, alk...(a) wrote:
> Hi,
> i am confused regarding the ADC/DAC interface implementation on FPGA.
> I have read a code where after serialising the input data of 16 bits
> in 16 clock cycles, the interface logic loops (in vain?) for another
> 16 cyles  before serialising the next data. can#t understand why? why
> the serialisation of the next data is not done immediately. moreover,
> should the serialisation clock rate be 16 higher than the data stream
> clock rate? Sorry but i could not find a documentation detailing all
> the synchronization mechanism.
> cheers :)

For details of this, look up a UART in a text book.

Here is a hint in the right direction.
Assume that data (digital or analog) is transmitted between two
at a certain rate, but asynchronously ie: no clock in the interface.
Can the receive clock be the same frequency of the transmit clock?
Assume there is no way to guarantee any relationship between the
two clocks. In fact, it is common for them to be slightly
different in frequency.

If the sample clock is 16X faster than the transmit, the middle
of a cycle is found when a start indication is found 8 times.
Then capturethe data values once every 16 times (because the
receive clockis 16X faster). With this slight differences in
can be tolerated - depending how many samples are taken between
realigning with a start bit.

Good Luck,
SynthWorks VHDL
First  |  Prev  | 
Pages: 1 2
Prev: Synplify synthesis error
Next: OFFSET and OFFSET out