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From: Don Lindsay on 21 Jan 2007 18:59 On 2007-01-14, Peter "Firefly" Lund <firefly(a)diku.dk> wrote: > It's > hard to create race conditions for an in-order pipelined machine with only > one clock domain. Almost every signal flows in the same direction and > each pipeline stage can be verified in isolation. IBM's first commercial RISC MPU (back before POWER 1) turned out to have a bug with fetchahead when the fetch crossed a VM page boundary. In general, the further apart the things that interact, the more funny issues there are. Aside from different clock domains, and bit skews, remote units may not even have identical voltage and temperature. Seymour Cray's designs were notorious for the money spent preventing ground bounce and signal reflection. So there's no shortage of ways to screw up, and my hat is off to every designer of every reliable product in the world. --- Don
From: "Peter "Firefly" Lund" on 22 Jan 2007 05:40
On Sun, 21 Jan 2007, Don Lindsay wrote: > On 2007-01-14, Peter "Firefly" Lund <firefly(a)diku.dk> wrote: >> It's >> hard to create race conditions for an in-order pipelined machine with only >> one clock domain. Almost every signal flows in the same direction and >> each pipeline stage can be verified in isolation. > > IBM's first commercial RISC MPU (back before POWER 1) turned out to > have a bug with fetchahead when the fetch crossed a VM page boundary. Yep, that's a nasty one. Page boundary crossings often have bugs. They are just not usually race conditions. -Peter |