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From: Marcelo Segura on 22 Feb 2010 12:45
Ok thanks all for your help.
I will try using diferent DCM for each MGT.
I hope that works.


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frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1
From: Ed McGettigan on 22 Feb 2010 19:07
On Feb 21, 6:03 pm, marcelo <u...(a)compgroups.net/> wrote:
> yes I understand but 500ps is to much for pcb delay, are 15cm.
> The idia is ti desing an ultra wideband transmiter using the MGT.
> I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo pulse), must be the same.
>
> ---
> frmsrcurl:http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-...

500pS is 7.7cm assuming 65pS/cm in typical FR-4 material.

I'm not a RF DSP expert, but why do you need two separate transmitters
for this design? What component are the transmitters connected to in
the system?

Ed McGettigan
--
Xilinx Inc.
From: Marcelo Segura on 22 Feb 2010 21:02
I need two transmiters, because I transmit BPSK pulse so positive and negative pulses.
The time bettwen pulses is 150 ns, so if I change the polarity of MGT, the output capacitor of the bord charge and discharge so I can't see the pulse at the output.
I don't know what hapen if I remove this capacitors.
thanks

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frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1
From: Ed McGettigan on 22 Feb 2010 21:34
On Feb 22, 6:02 pm, Marcelo Segura <u...(a)compgroups.net/> wrote:
> I need two transmiters, because I transmit BPSK pulse so positive and negative pulses.
> The time bettwen pulses is 150 ns, so if I change the polarity of MGT, the output capacitor of the bord charge and discharge so I can't see the pulse at the output.
> I don't know what hapen if I remove this capacitors.
> thanks
>
> ---
> frmsrcurl:http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-...

I don't understand what you mean here, is there a diagram somewhere on
the web that illustrates what you are attempting to do?

Ed McGettigan
--
Xilinx Inc.
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