Atmel AVR assembler
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From: Everett M. Greene on 13 Aug 2005 03:24 Herbert Kleebauer <klee(a)unibwm.de> writes: > Tauno Voipio wrote: > > Herbert Kleebauer wrote: > > > The registers are imaged in low memory addresses, > > but there is an important difference: most operations > > can use registers only. The plain memory locations can > > be used with loads and stores only. > > That's why I wrote: > > But from a marketing point of view it is much better to > say, AVR has 32 registers and a separate IO address space > than say it correctly: > > AVR doesn't have any registers and we have to use a part > of the memory address space for addressing the IO registers > and all the ALU operations like add, and, or, ... are > restricted to the first 32 memory locations (or if immediate > operands are used to the memory locations 16-31). The sad > thing is, that because of this marketing trick we have to use > a bad assembler syntax. > > The AVR architecture allows an implementation with separate > registers but can also implemented as a register less CPU with > ALU operations restricted to the first 32 memory locations. > I wouldn't be surprised if there are low cost versions (with > a lower clock speed) which don't have hardware registers. But > as I said, this are implementation details, the AVR architecture > uses memory mapped "registers" and therefore no registers (and > no IO instructions) are necessary in an AVR assembler. > > > Please check again a good reference book on > > RISC computer architectures. > > The fundamental characteristic of a RISC architecture is, > that only load/store instruction can access memory. In the > AVR architecture all ALU operation are performed on the > first 32 memory locations. Therefore I wouldn't call the AVR > architecture a RISC architecture. It is a register less > architecture with a short addressing mode for the zero > page. > > Which RISC processors do you know, which have a memory > mapped register set? Registers are logically just fast memory with a short form of addressing and predefined "names". There are usually arithmetic and logical operations that can be performed on registers that can't be performed (directly) on other locations. The AVR happens to map the "registers" to memory locations (as a number of other processors have done over the years).
From: Tauno Voipio on 13 Aug 2005 14:51
Herbert Kleebauer wrote: > But from a marketing point of view it is much better to > say, AVR has 32 registers and a separate IO address space > than say it correctly: The registers are in the register file which is a small RAM. The separate I/O address apage is just marketer's fog into the customer's eyes. In the same way, there are multiple names for the same basic instructions. It took some time for me to decode. The processor architecture is better than the desription. > The fundamental characteristic of a RISC architecture is, > that only load/store instruction can access memory. In the > AVR architecture all ALU operation are performed on the > first 32 memory locations. Therefore I wouldn't call the AVR > architecture a RISC architecture. It is a register less > architecture with a short addressing mode for the zero > page. > > Which RISC processors do you know, which have a memory > mapped register set? The registers have only memory mapped *images*. All the normal register operations are performed with register addressing. When all the RAM is internal to the processor chip, it's bloody difficult to tell which amount of register array is just a register bank and which amount is then memory used as registers. If the registers were regarded as a special zero page (without the traditional zero-page uses a la PDP-8), the instruction set would be described as a mess. The main effect of memory-mapping the registers and I/O is loss of some of the memory addressing capability. To me, it's a pretty traditional RISC (without delay slot problems) and extra possibility to index into the register bank. ---- The asssembly code is different from e.g. PDP-11 or Motorola 68xx and 68xxx, but it does not make it worse. There are selections done which seem to annoy you, but still there is no sense to fight it and claim that the other way is better. -- Tauno Voipio tauno voipio (at) iki fi |