EMC discussion
in [FPGA]
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From: Kolja Sulimma on 25 Mar 2010 14:13 On 25 Mrz., 02:57, Symon <symon_bre...(a)hotmail.com> wrote: > Hi Thomas, > 2) Only nutters have power planes. They use up valuable space in which > you could more profitably use a ground plane. Well, how do you create a low inductance path to the next capacitor? You do not necessarily need a full plane, but making sure there is a low inductance path quickly gets very cumbersome. A power plane is as good a reference for a signal as a ground plane and the PCB stack needs to be symmetric anyway. So what is the disadvantage of having a power plane as layer 2 when there is a gnd in layer N-2? Putting a GND plane there instead will waste more space with no gain (as you still need to route the power signals somewhere) and putting no plane in that layer will result in a bent board. Also, adjacent power planes provide multi GHz decoupling that is next to impossible to achieve with soldered capacitors. Kolja
From: glen herrmannsfeldt on 25 Mar 2010 14:41 John_H <newsgroup(a)johnhandwork.com> wrote: > On Mar 25, 10:55?am, Andy <jonesa...(a)comcast.net> wrote: >> Otherwise, suggesting that planes (partial or full) are not needed for >> power distribution to digital circuitry is ludicrous. > Consider: > Why do we need power planes? Are we trying to keep the "reference > rails" common between chips to a very high degree like we do with our > ground planes? Some drivers can pull up almost as much as down. > Here's an argument: distributed capacitance between the power and > ground planes are effective at the very high frequency end where > decoupling caps start to loose their effectiveness. Oops! Decoupling > at those very high frequencies off-chip doesn't appear to have much > effect [guru suggestion] and the larger the plane, the lower the self- > resonant frequency of that plane. If you have an 11" board, your > quarter wavelength is about 250MHz. You need to consider the power and ground planes as a radial transmission line. If you send a pulse in, the capactance per unit (radial) distance increases as r, and the inductance decreases as r. The series inductance is mostly determined near the via, as is the deficit in parallel capacitance. > Smaller planes are more effective > at pushing this high end of resonance out of the picture. Smaller > planes means smaller distributed capacitance. > I can understand the need for power planes in analog or balanced > circuits where the decoupling effects are still prevalent at the > discrete level. But for chip level? Maybe not after all. With the large currents required by some chips, it isn't so obvious. There are processors with Idd over 100 amps. > After my most recent board involvement I'm convinced that power > distribution would become less problematic with power distributed to > small, chip-local islands. The small islands do help distribute the > decoupling caps over an area, affecting inter-cap resonance issues. -- glen
From: James Salisbury on 25 Mar 2010 14:46 Thomas Entner wrote: > As I think, many FPGA-designers have also to deal with EMC, I hope > someone can help me here. We have currently some discussions (and > doubts) regarding EMC-topics. As many people have different opinions > on this subject, and it is quite hard to objectively verify, I would > like to ask for some comments about following: > > 1. Filtering of IC-supply-voltage > While it is quite standard to filter e.g. the PLL-supply voltages of a > FPGA, there are some suggestions to filter the supply-voltage of every > IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C. > (Consequently, this also means that every IC has it's own Vdd-island > in the power-plane.) Does this work? Please dont! you will just add to the number of caps you need. You only need to do this with sensitive analogue parts and PLLs of FPGAs > > 2. Return-path on Vdd-plane > It is pretty clear that a solid ground-plane is required for return- > path of I/O-signals. Most people also agree, that a power-plane will > also do this job. But is this only because of the bypass-caps? Or is > the "native" return-current flowing on ground when the output-driver > is sinking and on Vdd when the output-driver is sourcing (assuming a > high-impedance destination), i.e. it would be perfect to have both > planes close to the signal-line? Yes, the initial pulse of power at high edge rates first comes from on chip capacitance then from the power plane. > > 3. Shields of connectors, chassis ground > Most PCBs have one or more connectors with shields (e.g. USB, RJ45, > VGA, RS-232,...) Do you connect these directly to circuit-ground? Or > with C and R in parallel? Or do you have some kind of "frame-ground"? > Have you the mounting holes grounded to the chassis? All or just one? > Shields, mount the connectors with fingers touching a metallic box encloseing the circuit. Ensure that the ground planes are also bolted inside the box to the ground plane at regular intervals. Ensure that the plateing on the inside of the box is conductive. To check that it is conductive make a brush out of some 16/0.2 mm wire, strip 25mm, and 12.5 mm from the end bend through 90 degrees. Use your meter on continuity and gently use the two brushes as probes. If you do not get a low reading with light pressure, reject the case. Lots of good stuff here http://www.compliance-club.com/ Particularly in the Keith Armstrong section James
From: John_H on 25 Mar 2010 14:55 On Mar 25, 2:41 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > > Some drivers can pull up almost as much as down. The issue isn't direct return current to the VCC drive transistor because the current needs to head through the package to the VCC pin to the power island in the first place which may be referenced to the wrong plane anyway. With effective decoupling near the source, the return current goes from the driver to the on-chip decoupling, through the package to the off-chip decoupling, to the plane(s) the signal references against. The smaller the overall current loops, the smaller the EMI and crosstalk. Do you want your huge current spikes to force your ground and power planes to both fluctuate at equal amplitudes? Or would you prefer that your ground is more solid and the power plane sloppier? The answers aren't obvious otherwise we wouldn't have guidelines that specify not only a power plane but one 1uF, one 0.1uF, and one 0.01uF capacitor per power and ground pin pair (of which there are 27 on the part). Bogus guidelines.
From: glen herrmannsfeldt on 25 Mar 2010 15:57
John_H <newsgroup(a)johnhandwork.com> wrote: > On Mar 25, 2:41?pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: >> Some drivers can pull up almost as much as down. ? > The issue isn't direct return current to the VCC drive transistor > because the current needs to head through the package to the VCC pin > to the power island in the first place which may be referenced to the > wrong plane anyway. With effective decoupling near the source, the > return current goes from the driver to the on-chip decoupling, through > the package to the off-chip decoupling, to the plane(s) the signal > references against. The smaller the overall current loops, the > smaller the EMI and crosstalk. Well, in the TTL days everything was ground referenced. With CMOS that is much less true. In any case, it is series inductance (bond wires, package pins, and PC traces) > Do you want your huge current spikes to force your ground and power > planes to both fluctuate at equal amplitudes? Or would you prefer > that your ground is more solid and the power plane sloppier? If I remember the early CMOS right, it was symmetric. The switch point was at (Vss+Vdd)/2. As far as I know, that isn't true anymore. In any case, there isn't much we can do about the inductances inside the package. Once it gets outside, we need low enough inductance until it gets to a large enough capacitance. > The answers aren't obvious otherwise we wouldn't have guidelines that > specify not only a power plane but one 1uF, one 0.1uF, and one 0.01uF > capacitor per power and ground pin pair (of which there are 27 on the > part). Bogus guidelines. -- glen |