EMC discussion
in [FPGA]
|
From: Symon on 25 Mar 2010 15:58 On 3/25/2010 6:13 PM, Kolja Sulimma wrote: > On 25 Mrz., 02:57, Symon<symon_bre...(a)hotmail.com> wrote: >> Hi Thomas, >> 2) Only nutters have power planes. They use up valuable space in which >> you could more profitably use a ground plane. > Well, how do you create a low inductance path to the next capacitor? > You do not necessarily need a full plane, but making sure there is a > low inductance > path quickly gets very cumbersome. You use copper pours and puddles around the IC to link its bypass capacitors. > A power plane is as good a reference for a signal as a ground plane > and the PCB stack > needs to be symmetric anyway. So what is the disadvantage of having a > power plane as > layer 2 when there is a gnd in layer N-2? 1) The stack up does not need to be symmetrical wrt to planes and signal layers. However, you should make the substrates symmetrical. I have made several boards that aren't plane symmetrical. Talk to your PCB vendor. (Some of these boards were about 12x8 inches and didn't warp.) 2) When a signal trace passes from layer 1 to layer N-1, its reference plane has now changed. If this signal has a fast rise time, you have to use a bypass capacitor nearby, with its attendant inductance, and via inductance. With two ground planes, a regular via is enough. 3) You make an interesting point when you say that a power plane is as good as a ground plane as a reference. This is true. The problem comes that you now have two references in your system, and they will have some small noise voltage between them. You can reduce this to a small amount of noise with capacitors, but for each power plane, you have to do this. With multiple ground planes, they are all bonded together with the ground vias in your board. > Putting a GND plane there instead will waste more space with no gain > (as you still need to > route the power signals somewhere) and putting no plane in that layer > will result in a bent board. Indeed, you need to put the powers somewhere. I recommend routing them all on a couple of dedicated layers away from signal traces. On an FPGA with at least 1.2V, 1.8V, 2.5V and 3.3V rails, which of these are you suggesting will be on a plane? All of them? (Again, the bent board thing is a fallacy, I have found.) > > Also, adjacent power planes provide multi GHz decoupling that is next > to impossible to achieve with > soldered capacitors. > We've been here before. It has a small amount of capacitance, which doesn't help you because the multi-GHz can't get up the vias and balls into the dice. Think of it this way, the reason a soldered capacitor doesn't give you multi-GHz is the fact that you have to connect to it. Actually in the ceramic of the cap is multi-GHz. It's the same with connecting your chips to a adjacent-plane-made capacitor. Of course, what this arrangement does also provide is the possibility of multi-GHz resonances in your power planes. Lovely. Using a ground plane where ever a reference plane is needed makes the SI design very simple indeed. > > Kolja
From: Symon on 25 Mar 2010 16:11 On 3/25/2010 6:04 PM, Andy wrote: > I agree that power islands, where required, are OK, but it was not > clear what your original statement was recommending. Under what > circumstances power islands are required is up for debate. > > Whether they are used as signal shield layers (for HF return currents) > is dependent up on the application, whether traces can be routed > without crossing between different islands, and whether or not adding > additional layers for additional ground planes is a good trade. > > No sir, I'm just part of the common 'we' (the same group you adressed > as 'anyone'). Are you the Royal Symon? > > Andy Hi Andy, You appear to have overlooked one of my queries. I'm interested in your response. Would you have a plane for every supply? I'm interested, because you posted that "suggesting that planes (partial or full) are not needed for power distribution to digital circuitry is ludicrous". Thanks, HRH Symon. p.s. I thought 'anyone' was singular. :-)
From: Thomas Entner on 25 Mar 2010 16:26 Thank you everyone for the comments, it is an very interesting reading. I already got a lot of input for a new PCB-design, from which we will do some variants to check which EMC-solution works best. Looks like we need more variants than originally planned... Thomas
From: Andy on 25 Mar 2010 16:27 On Mar 25, 3:11 pm, Symon <symon_bre...(a)hotmail.com> wrote: > On 3/25/2010 6:04 PM, Andy wrote: > > > I agree that power islands, where required, are OK, but it was not > > clear what your original statement was recommending. Under what > > circumstances power islands are required is up for debate. > > > Whether they are used as signal shield layers (for HF return currents) > > is dependent up on the application, whether traces can be routed > > without crossing between different islands, and whether or not adding > > additional layers for additional ground planes is a good trade. > > > No sir, I'm just part of the common 'we' (the same group you adressed > > as 'anyone'). Are you the Royal Symon? > > > Andy > > Hi Andy, > > You appear to have overlooked one of my queries. I'm interested in your > response. > > Would you have a plane for every supply? > > I'm interested, because you posted that "suggesting that planes (partial > or full) are not needed for power distribution to digital circuitry is > ludicrous". > > Thanks, HRH Symon. > > p.s. I thought 'anyone' was singular. :-) By 'plane', do you mean an entire PWB layer? In that case, no, an entire layer is not always necessary (unless the circuitry served by the power supply is distributed all over the board anyway.) If by 'plane', you mean a broad area flooded with copper, but not necessarily an entire PWB layer, then my answer is yes, a broad, flooded area is necessary for power distribution to digital circuitry. Andy
From: Nico Coesel on 25 Mar 2010 19:02
Symon <symon_brewer(a)hotmail.com> wrote: >On 3/25/2010 1:10 AM, Thomas Entner wrote: >> As I think, many FPGA-designers have also to deal with EMC, I hope >> someone can help me here. We have currently some discussions (and >> doubts) regarding EMC-topics. As many people have different opinions >> on this subject, and it is quite hard to objectively verify, I would >> like to ask for some comments about following: >> >> 1. Filtering of IC-supply-voltage >> While it is quite standard to filter e.g. the PLL-supply voltages of a >> FPGA, there are some suggestions to filter the supply-voltage of every >> IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C. >> (Consequently, this also means that every IC has it's own Vdd-island >> in the power-plane.) Does this work? >> >> 2. Return-path on Vdd-plane >> It is pretty clear that a solid ground-plane is required for return- >> path of I/O-signals. Most people also agree, that a power-plane will >> also do this job. But is this only because of the bypass-caps? Or is >> the "native" return-current flowing on ground when the output-driver >> is sinking and on Vdd when the output-driver is sourcing (assuming a >> high-impedance destination), i.e. it would be perfect to have both >> planes close to the signal-line? >> >> 3. Shields of connectors, chassis ground >> Most PCBs have one or more connectors with shields (e.g. USB, RJ45, >> VGA, RS-232,...) Do you connect these directly to circuit-ground? Or >> with C and R in parallel? Or do you have some kind of "frame-ground"? >> Have you the mounting holes grounded to the chassis? All or just one? >Hi Thomas, > >1) Yes. That will keep noise from coupling between devices. >2) Only nutters have power planes. They use up valuable space in which >you could more profitably use a ground plane. OK if you have enough decoupling on every pin. >3) Bond it all together. Unless you have to have isolation from >dangerous voltages. I feel more comfortable to put a bead between the shield and the ground. Keeps HF current inside / breaks HF pickup loops when wiring equipment together. >If anyone wants to disagree with this advice, I want a specific, first >person example where what I suggest is wrong. I don't want to hear what >some 'guru' told you on a course you paid for. :-) > >Symsx. > > > -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico(a)nctdevpuntnl (punt=.) -------------------------------------------------------------- |