I'd rather switch than fight!
in [FPGA]
|
From: Patrick Maupin on 15 Apr 2010 18:30 On Apr 15, 4:58 pm, Jonathan Bromley <s...(a)oxfordbromley.plus.com> wrote: > Of course, there's also a ton of stuff that Verilog can do > but VHDL can't. And it's rarely a good idea to judge any > language by a laundry-list of its feature goodies. Agreed completely. > But it is NEVER a good idea to trivialize the discussion. Well, you have to talk to others about that. Somebody else brought up the stupid Verilog contest, and David, apparently agreeing with some sentiment there, said: > Another famous contest involved a C and Ada comparison. It took the Ada > more than twice as long as the C team to write their code, but it took > the C team more than ten times as long to debug their code. To which the only sane answer was my flippant "it's not the same" (and, of course the very first thing that's not the same is who the purported winner was). I don't think either contest is worth a hoot, but I do find it interesting that you found it necessary to pen a long response to my flippant response, yet found it acceptable to ignore the statement about the C vs. ADA contest. Regards, Pat
From: Jonathan Bromley on 16 Apr 2010 03:47 On Apr 15, 11:30 pm, Patrick Maupin <pmau...(a)gmail.com> wrote: > I do find it interesting that you found it necessary to pen > a long response to my flippant response, yet found it acceptable to > ignore the statement about the C vs. ADA contest. I try to write on things I know something about :-) I am painfully familiar with the Cooley Verilog-vs-VHDL nonsense, but know nothing about that C-Ada contest. In any case, I wasn't particularly responding to you. I took an opportunity to say something I've wanted to say for a long time about an exceedingly faulty part of the HDL mythology. -- Jonathan Bromley
From: Paul on 16 Apr 2010 03:47 On 15 Apr, 22:33, Jan Decaluwe <j...(a)jandecaluwe.com> wrote: > For example, with MyHDL you will also have to learn about latch > inference and how to avoid "unwanted latches". However, just like in > VHDL/Verilog there is a much better solution for this than using a > limited HDL: use a clocked process template by default. :-) In a rather long thread about vhdl Vs verilog, you seem to have placed your can opener on another tin of worms marked one process state machines vs two. What you trying to do, crash google's servers?
From: David Brown on 16 Apr 2010 05:15 On 15/04/2010 23:31, Muzaffer Kal wrote: > On Thu, 15 Apr 2010 14:21:37 -0700 (PDT), Patrick Maupin > <pmaupin(a)gmail.com> wrote: > >> On Apr 15, 3:12 pm, David Brown<da...(a)westcontrol.removethisbit.com> >> wrote: >> >>> Another famous contest involved a C and Ada comparison. It took the Ada >>> more than twice as long as the C team to write their code, but it took >>> the C team more than ten times as long to debug their code. >> >> Well, this isn't at all the same then. The Verilog teams got working >> designs, and the VHDL teams didn't. > > There are two issues to consider. One is the relative times of writing > the codes vs debugging ie if writing took 5 hours and debugging 10 > minutes (unlikely) then C still wins. Which brings the second issue: > it is very likely that the programming contest involved a "larger" > design to be finished. If I am remembering correctly RTL was an async > reset, synchronously loadable up-down counter which is a "smallish" > project. If programming contest involved something more "involved" it > still points to the benefit of strong typing and other features of > Ada/VHDL etc. The contest in question was a substantial programming project over a longer period - weeks rather than hours. I don't remember how much time was actually spend on debugging rather than coding, but it certainly worked out that the Ada team were finished long before the C team.
From: David Brown on 16 Apr 2010 05:31
On 16/04/2010 00:30, Patrick Maupin wrote: > On Apr 15, 4:58 pm, Jonathan Bromley<s...(a)oxfordbromley.plus.com> > wrote: > >> Of course, there's also a ton of stuff that Verilog can do >> but VHDL can't. And it's rarely a good idea to judge any >> language by a laundry-list of its feature goodies. > > Agreed completely. > >> But it is NEVER a good idea to trivialize the discussion. > > Well, you have to talk to others about that. Somebody else brought up > the stupid Verilog contest, and David, apparently agreeing with some > sentiment there, said: > I wasn't agreeing with the validity of the Verilog/VHDL contest, although I suppose by not saying that, it looked like I agreed with it. It would have been more useful if I'd given a little more detail. The Ada / C contest was over a much longer time scale, using a real-world project - and thus is a much more valid contest (though obviously, like any test or benchmark, you can't apply it thoughtlessly to other contexts). It was an indication of where the stronger typing and generally stricter compiler and language was demonstrated to give a faster development time in a real case. I can't say whether those results could carry over to a comparison between VHDL and Verilog, or how much the results are the effect of strong typing. But since VHDL is often though of as being a similar style of language to Ada, and Verilog is similarly compared to C, it may be of interest. I couldn't find references to the study I was thinking of, but I found one in a similar vain: <http://www.adaic.org/whyada/ada-vs-c/cada_art.html#conclusion> Of course, I haven't scoured the net looking for enough articles to give a balanced view here. So if my comments here are of interest or use to anyone, that's great - if not, I'll not complain if you ignore them! >> Another famous contest involved a C and Ada comparison. It took the Ada >> more than twice as long as the C team to write their code, but it took >> the C team more than ten times as long to debug their code. > > To which the only sane answer was my flippant "it's not the > same" (and, of course the very first thing that's not the same is who > the purported winner was). I don't think either contest is worth a > hoot, but I do find it interesting that you found it necessary to pen > a long response to my flippant response, yet found it acceptable to > ignore the statement about the C vs. ADA contest. > > Regards, > Pat |