Picking N-th ready element (e.g. in an OOO scheduler)
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From: nedbrek on 17 Jul 2010 17:08 "Andy Glew" <"newsgroup at comp-arch.net"> wrote in message news:BsedncmAl52kRdzRnZ2dnUVZ_oOdnZ2d(a)giganews.com... > > Now, please don't get insulted when I say you are a crank. Cranks are my > people. I'm a crank. Cranks occasionally come up with good ideas. Hehe, reminded me of this cartoon: http://sydneypadua.com/2dgoggles/lovelace-and-babbage-vs-the-organist-pt-1/ I can be a crank, as long as I am not the "Itanium crank". Anything but that, please. :P Ned
From: Andy Glew "newsgroup at on 17 Jul 2010 18:40 On 7/17/2010 10:03 AM, jacko wrote: > No dependence on DFET. The dual wire thing is not dependent on it > either. The dual wires just make the metal routing between the drains > longer and so with higher resistance. Any metal T node works like a > potential divider. It's just to take advantage of any parasitic > resistance, or stripline characteristic impedence (at high speed and > the longer route) versus resistance. > > So back to pickers as that is a process (metal layer) factor, not a > logical gate factor.. You've just said several things that are red flags in modern VLSI. "Potential divider". => power wasting, unreliable in the presence of variation. "process (metal layer) factor, not a logical gate factor". => the whole trend of the last decade in VLSI design has been to wind ourselves back to just thinking in terms of logical gates, to avoid nearly all of the neat tricks dependent on particular process characteristics. > I would avoid multiple picking from the same queue. And now you have missed the whole point of the discussion. Or, rather, you are talking about a different scheduler design - myltiple 1 pickers, rather than 1 picker picking N ready elements of priority 1..N. Your ideas may be good, but it is immensely frustrating to go around and around like this. If you want to change to a different topic, say so.
From: Andy Glew "newsgroup at on 17 Jul 2010 18:45 On 7/17/2010 2:08 PM, nedbrek wrote: > "Andy Glew"<"newsgroup at comp-arch.net"> wrote in message > news:BsedncmAl52kRdzRnZ2dnUVZ_oOdnZ2d(a)giganews.com... >> >> Now, please don't get insulted when I say you are a crank. Cranks are my >> people. I'm a crank. Cranks occasionally come up with good ideas. > > Hehe, reminded me of this cartoon: > http://sydneypadua.com/2dgoggles/lovelace-and-babbage-vs-the-organist-pt-1/ > > I can be a crank, as long as I am not the "Itanium crank". Anything but > that, please. :P Better a crank than a cog! (Hey, that's my new motto.)
From: MitchAlsup on 17 Jul 2010 18:51 On Jul 17, 11:19 am, Andy Glew <"newsgroup at comp-arch.net"> wrote: > Plus your response to Mitch: > Dual gate FETs with differential doping and antiphase. (I've thought > about such stuff: if you could make a dual gate that was well aligned > and matched, you could have an XOR that is cheaper than a NAND gate. > But the experts always tell me that, while in theory it might work, in > practice with variations and tolerances it has no chance.) AMD has a patent on such an XOR gate using two raised FIN FET diffusion channels, one side doped N the other doped P. I suspect ohers have similar patents on different transistor technologies that amount ot the same things. But the technology discussion taking place herein, requires nothing outside of pure CMOS and for the most part pure logic-gates. Mitch
From: Andy Glew "newsgroup at on 17 Jul 2010 20:33
On 7/17/2010 3:40 PM, Andy Glew wrote: > On 7/17/2010 10:03 AM, jacko wrote: > You've just said several things that are red flags in modern VLSI. > "process (metal layer) factor, not a logical gate factor". => the whole > trend of the last decade in VLSI design has been to wind ourselves back > to just thinking in terms of logical gates, to avoid nearly all of the > neat tricks dependent on particular process characteristics. There are a very, very, few places in modern VLSI where analog tricks can be used. Sense amps in arrays. The self timed parts of FPGAs (and even that uis under attack). Yes, one can easily imagine making broader use of such tricks. E.g. a friend of mine, Wen-Mei's other early hardware student, developed a logic family that used sense amps between complementary networks. You just have to be a very, Very, VERY good circuit designer, and have very, Very, VERY good justification, to even get your foot into the conference room door to be listened to wrt this sort of thing. Probably harder to get listened to than even asynchronous logic. |