From: jacko on
On 18 July, 22:19, MitchAlsup <MitchAl...(a)aol.com> wrote:
> On Jul 17, 8:33 pm, jacko <jackokr...(a)gmail.com> wrote:
>
> > A resistive metal wire metal layer called
>
> Schematics or <just stop>

N-picking is silly, 1-picking on N ques is not.

Schematics of a 1 picker you already have.

I have already supplied you with a schematic symbol of the DISCO-FET
titled Q1.

Schematics of a logic interconnect technology are 'obvoius', pity you
have dificulty in drawing a close pair of lines/or a thicker one on an
existing schematic.

The End.
From: Andy Glew "newsgroup at on
On 7/18/2010 2:48 PM, jacko wrote:
> On 18 July, 22:19, MitchAlsup<MitchAl...(a)aol.com> wrote:
>> On Jul 17, 8:33 pm, jacko<jackokr...(a)gmail.com> wrote:
>>
>>> A resistive metal wire metal layer called
>>
>> Schematics or<just stop>
>
> N-picking is silly, 1-picking on N ques is not.
>
> Schematics of a 1 picker you already have.
>
> I have already supplied you with a schematic symbol of the DISCO-FET
> titled Q1.
>
> Schematics of a logic interconnect technology are 'obvoius', pity you
> have dificulty in drawing a close pair of lines/or a thicker one on an
> existing schematic.
>
> The End.

Yes, The End.

If everything that you were blathering about amounted to making some
existing wires "a close pair of lines", then you weren't even talking
about the logic. You were just making the gates more efficiently.
Supposedly.

If you think that supplying "a schematic symbol of the DISCO-FET" is a
contribution, you are thinking magically.

And while there is value to talking about "N-picking is silly, 1-picking
on N queues is not", saying it is silly reflects on you - since Mitch
has already shown circuits that are surprisingly efficient at small
scale, while this thread started off with a way of making it efficient
at large scale.

The only reason this discussion lasted as long as it did was that you
were unable to make clear statements such as the above earlier. Now that
I can see clearly what you were talking about, yes, it truly was wasted
bandwidth.
From: jacko on
On 21 July, 06:17, Andy Glew <"newsgroup at comp-arch.net"> wrote:
> On 7/18/2010 2:48 PM, jacko wrote:
>
>
>
>
>
> > On 18 July, 22:19, MitchAlsup<MitchAl...(a)aol.com>  wrote:
> >> On Jul 17, 8:33 pm, jacko<jackokr...(a)gmail.com>  wrote:
>
> >>> A resistive metal wire metal layer called
>
> >> Schematics or<just stop>
>
> > N-picking is silly, 1-picking on N ques is not.
>
> > Schematics of a 1 picker you already have.
>
> > I have already supplied you with a schematic symbol of the DISCO-FET
> > titled Q1.
>
> > Schematics of a logic interconnect technology are 'obvoius', pity you
> > have dificulty in drawing a close pair of lines/or a thicker one on an
> > existing schematic.
>
> > The End.
>
> Yes, The End.
>
> If everything that you were blathering about amounted to making some
> existing wires "a close pair of lines", then you weren't even talking
> about the logic. You were just making the gates more efficiently.
> Supposedly.

The logic library will need the output wire, making into 2 output
wires and revoval of the metal routing between the two drive drain's,
but it will still be the gate type is was.

> If you think that supplying "a schematic symbol of the DISCO-FET" is a
> contribution, you are thinking magically.

We'll one tribune deserves another.

> And while there is value to talking about "N-picking is silly, 1-picking
> on N queues is not", saying it is silly reflects on you - since Mitch
> has already shown circuits that are surprisingly efficient at small
> scale, while this thread started off with a way of making it efficient
> at large scale.

Yes and then those picked instructions will then have contention for
the register pool.

> The only reason this discussion lasted as long as it did was that you
> were unable to make clear statements such as the above earlier. Now that
> I can see clearly what you were talking about, yes, it truly was wasted
> bandwidth.

End of Titles.