The Perfect Computer - 36 bits?
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From: Quadibloc on 27 Mar 2007 20:44 Nick Maclaren wrote: > In article <1174992323.115637.216890(a)p15g2000hsd.googlegroups.com>, > "Quadibloc" <jsavard(a)ecn.ab.ca> writes: .. > |> I find this sad, as I would have liked to have a relatively elegant > |> and clean, but conventional, microprocessor available, such as the > |> 68020 architecture. ColdFire omits indexed memory access, which means > |> it omits too much. > > There is no reason that a RISC architecture cannot have a clean ISA, .. Of course there isn't; RISC architectures almost by definition have clean ISAs. However, some CISC architectures do not. Specifically, the x86 architecture does not; since it is the *only* CISC architecture broadly available at this time, the lack which I refer to exists. > and there is no particular reason for saying that indexed access must > be built-in to the basic instruction format. While needing a separate > instruction for indexing makes the code bulkier, that hasn't been a > major issue for over a decade. Memory bandwidth is still an issue. Yes, instructions cache well, so they're a minor part of it, but anything that conserves this bandwidth and conserves (shared!) L2 cache space is helpful. > It is a great pity that the new RISC systems (as distinct from previous > inventions of the approach) concentrated entirely on making the hardware > simple, often at the cost of making the software hell to get right. > Which is one of the reasons that many aspects of modern software are > so much worse than they were 25 years ago. > > It wasn't, and it isn't, necessary. I'll certainly agree that RISC doesn't have to be like the Itanium. John Savard
From: Quadibloc on 27 Mar 2007 20:49 Andrew Swallow wrote: > We can certainly have a nice debate as to whether anything containing > floating point hardware is RISC. At one time, that was true, back when the RISC model called for every instruction to take one cycle. I think, however, that this issue is now dead; many architectures with floating-point hardware are generally accepted as RISC. The boundary between RISC and CISC seems to be the presence or absence of instructions like MPY 5,PROPOR(3) that is, add the contents of index register 3 to the address of the array PROPOR, and multiply the contents of general register 5 by the contents of the memory location which that indicates. RISC is load store with separate address calculation instructions, and lots of registers, and all instructions that perform a calculation operating between registers. CISC is instructions like the one above. CISC can be tidy and elegant - System/360, for example. John Savard
From: Charles Shannon Hendrix on 28 Mar 2007 01:56 ["Followup-To:" header set to alt.folklore.computers.] >> LSI-11 customers, PDP-8 >>customers and the VAX/VMS customers. Eventually the company runs >>out of customers. > > You are talking about the 90s when the plan was to strip the company > down to its help desk, which is the only piece that Compaq wanted. Sort of. The late 90s was when the stripping occured. But dropping support for those customers mentioned above happened long before this. Even in the very early 90s, DEC was putting their older systems down, and people who came out to talk to you were almost hostile when you started to ask about VAX or PDP systems. They pushed Alpha pretty hard, even when it made no sense. For awhile they still pushed VMS, but not for long. I was at a DEC UNIX shop from 1995-1998, and I was never impressed with their support of those systems. Some things about the hardware and OS were really nice, but along with it came extreme frustrations of one kind or another, and they were pretty much unresponsive about the problems. DEC finally thumbed its nose at one too many third parties and they abandoned DEC for Sun en-masse. Of course, I hear it was part of a plan, so I guess it makes sense even while not making much sense. > What is really sad is that they trashed it and then HP seems to have > completed the job. True, but I see this as a fairly long process that started before Compaq got involved, and long before Carly. -- shannon "AT" widomaker.com -- ["There are nowadays professors of philosophy, but not philosophers." ]
From: Charles Shannon Hendrix on 28 Mar 2007 01:59 ["Followup-To:" header set to alt.folklore.computers.] On 2007-03-27, John Byrns <byrnsj(a)sbcglobal.net> wrote: > I always thought DEC should have extended the PDP-11 to 32 bits and > skipped the VAX. I don't know about skipping the VAX, since it was interesting in its own right, but it would have been nice to see a 32-bit PDP-11. You know... which modern FPGAs, someone could actually do it and see how well it would have worked. -- shannon "AT" widomaker.com -- ["There are nowadays professors of philosophy, but not philosophers." ]
From: Charles Shannon Hendrix on 28 Mar 2007 02:04
["Followup-To:" header set to alt.folklore.computers.] On 2007-03-27, David Kanter <dkanter(a)gmail.com> wrote: > A much more reasonable, and possibly true, assertion would be that the > advantage of RISC architectures decreased over time. However, even as > late as the Pentium 1, there was a huge advantage for RISC > architectures. With the Pentium Pro that became less clear, although > RISCs still ruled the roost for FP heavy applications. I think there is another issue to think about: A lot of CISC CPUs have RISC cores. Basically they are RISC CPUs with a layer of CISC emulation. Alternately, there are CISC CPUs that also have a fairly complete set of RISC or RISC-ish instructions that you can use. Then there are the "RISC" CPUs which have amazingly complex ISAs in spite of their name. Some of the line are much more blurred than they used to be. -- shannon "AT" widomaker.com -- ["There are nowadays professors of philosophy, but not philosophers." ] |