From: Telenochek on
Hi all,



I have an SDRAM interface buried deep inside the hierarchy.
I was able to instantiate OBUF for the control & address signals and
traverse the hierarchy from the UCF file to tie the signals to the
FPGA pins.

However, when I try to do something similar for the IOBUFs, I get an
error of the type



INFO:NgdBuild:889 - Pad net 'eight_chan_gen/u1/external_sdram/U1/
DQ<0>' is not connected to an external port in this design. A new
port 'DQ<0>' has been added and is connected to this signal.



Example of a successful OBUF:

--VHDL file (inside the submodule)

obuf_sdram_a0: OBUF port map (O => sdram_a0, I => A(0));

--.UCF file

NET "eight_chan_gen/u1/external_sdram/U1/A<0>" LOC="D14";



Example of a failing IOBUF:

--VHDL file (inside the submodule)

IOBUF_inst0 : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "LVCMOS25",
SLEW => "SLOW")
port map (
O => DQ_OUT(0),
IO => DQ(0),
I => DQ_IN(0),
T => nDQ_OE);

--UCF file

NET "eight_chan_gen/u1/external_sdram/U1/DQ<0>" LOC = "A4";



Any suggestions?



Thanks in advance!
From: gabor on
On Sep 8, 12:13 pm, Telenochek <elet.mir...(a)gmail.com> wrote:
> Hi all,
>
> I have an SDRAM interface buried deep inside the hierarchy.
> I was able to instantiate OBUF for the control & address signals and
> traverse the hierarchy from the UCF file to tie the signals to the
> FPGA pins.
>
> However, when I try to do something similar for the  IOBUFs, I get an
> error of the type
>
> INFO:NgdBuild:889 - Pad net 'eight_chan_gen/u1/external_sdram/U1/
> DQ<0>' is not connected to an external port in this design.  A new
> port 'DQ<0>' has been added and is connected to this signal.
>
> Example of a successful OBUF:
>
> --VHDL file (inside the submodule)
>
> obuf_sdram_a0:    OBUF port map (O => sdram_a0, I => A(0));
>
> --.UCF file
>
> NET "eight_chan_gen/u1/external_sdram/U1/A<0>" LOC="D14";
>
> Example of a failing IOBUF:
>
> --VHDL file (inside the submodule)
>
>    IOBUF_inst0 : IOBUF
>    generic map (
>       DRIVE => 12,
>       IOSTANDARD => "LVCMOS25",
>       SLEW => "SLOW")
>    port map (
>         O => DQ_OUT(0),
>       IO => DQ(0),
>       I => DQ_IN(0),
>       T => nDQ_OE);
>
> --UCF file
>
> NET "eight_chan_gen/u1/external_sdram/U1/DQ<0>"   LOC = "A4";
>
> Any suggestions?
>
> Thanks in advance!

How did you instantiate the modules between this and the top?
Are all connections "inout" through the whole hierarchy including
the top level port?
From: Ed McGettigan on
On Sep 8, 9:13 am, Telenochek <elet.mir...(a)gmail.com> wrote:
> Hi all,
>
> I have an SDRAM interface buried deep inside the hierarchy.
> I was able to instantiate OBUF for the control & address signals and
> traverse the hierarchy from the UCF file to tie the signals to the
> FPGA pins.
>
> However, when I try to do something similar for the  IOBUFs, I get an
> error of the type
>
> INFO:NgdBuild:889 - Pad net 'eight_chan_gen/u1/external_sdram/U1/
> DQ<0>' is not connected to an external port in this design.  A new
> port 'DQ<0>' has been added and is connected to this signal.
>
> Example of a successful OBUF:
>
> --VHDL file (inside the submodule)
>
> obuf_sdram_a0:    OBUF port map (O => sdram_a0, I => A(0));
>
> --.UCF file
>
> NET "eight_chan_gen/u1/external_sdram/U1/A<0>" LOC="D14";
>
> Example of a failing IOBUF:
>
> --VHDL file (inside the submodule)
>
>    IOBUF_inst0 : IOBUF
>    generic map (
>       DRIVE => 12,
>       IOSTANDARD => "LVCMOS25",
>       SLEW => "SLOW")
>    port map (
>         O => DQ_OUT(0),
>       IO => DQ(0),
>       I => DQ_IN(0),
>       T => nDQ_OE);
>
> --UCF file
>
> NET "eight_chan_gen/u1/external_sdram/U1/DQ<0>"   LOC = "A4";
>
> Any suggestions?
>
> Thanks in advance!

If the net had been succesfully brought all the way to a port at the
top level of the design the name should not include hierarchy.

Ed McGettigan
--
Xilinx Inc.
From: Telenochek on
I would prefer to avoid bringing all the ports to top level.

I should be able to LOC constrain any internal signal of choice?
From: gabor on
On Sep 9, 10:46 am, Telenochek <elet.mir...(a)gmail.com> wrote:
> I would prefer to avoid bringing all the ports to top level.
>
> I should be able to LOC constrain any internal signal of choice?

You should be able to, theoretically, but in the end it is useful
to have access to the board pins from the top level module as
it makes it much easier to attach them to the SDRAM simulation
model in your testbench.