VLIW pre-history
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From: Eric Smith on 15 May 2007 02:54 I wrote: > That doesn't explain how I can look at a piece of hardware and > definitively state that it is or is not VLIW. I think it should > be possible to do that without looking at the software. John L wrote: > Well, like I said, try programming it by hand, and if you can't, it > must be VLIW. Eugene Miya wrote: > So gee Eric, does that mean we are going to dust off the Multiflow and > grab Josh to reboot it? 8^) Sure, let's do it! :-)
From: Eric Smith on 15 May 2007 02:56 Quadibloc wrote: > But I would think that there is a very simple definition of VLIW. Once upon a time I thought that of RISC, too. But that war has been lost. > Instructions explicitly code for superscalar operation. Sounds reasonable to me. So an i860 qualifies? Eric
From: Eugene Miya on 15 May 2007 12:57 In article <qhps52r304.fsf(a)ruckus.brouhaha.com>, Eric Smith <eric(a)brouhaha.com> wrote: >> That doesn't explain how I can look at a piece of hardware and >> definitively state that it is or is not VLIW. I think it should >> be possible to do that without looking at the software. I wondered the same thing the first time I saw one. Talk to me off line about that (as in "where"). It was just a board to me. >John L wrote: >> Well, like I said, try programming it by hand, and if you can't, it >> must be VLIW. > >Eugene Miya wrote: >> So gee Eric, does that mean we are going to dust off the Multiflow and >> grab Josh to reboot it? 8^) > >Sure, let's do it! :-) I don't recall what the state of the disks on the system were. --
From: Quadibloc on 16 May 2007 03:28 Eric Smith wrote: > Quadibloc wrote: > > But I would think that there is a very simple definition of VLIW. > > Once upon a time I thought that of RISC, too. But that war has been > lost. > > > Instructions explicitly code for superscalar operation. > > Sounds reasonable to me. So an i860 qualifies? .. I don't know enough about the i860 to answer that at the moment. .. Looking at the manual for the AP-120B, it had 64-bit instructions that coded for an "S-pad" operation, a floating adder operation, and a floating multiplier operation. I would say it *definitely* qualifies as a VLIW architecture. Even if that term only arose later with machines like the Cyberplus, this is the same sort of thing, but in a smaller version. (The assembly language for it obscures the fact that adder and multiplier instructions are really part of the same instruction word.) John Savard
From: Quadibloc on 16 May 2007 03:46
Greg Lindahl wrote: > Sounds like ordinary microcode on a pipelined processor. The FPS > AP120B array processor (which didn't come along until the early 80s) > let you microcode it directly. But since it's just microcode, it's not > exactly a novel idea, it's just unusual today to think of directly > programming it that way. I looked at the FPS AP-120B manual, and I think that it definitely qualifies as VLIW. A 64-bit instruction had three fields; one operated on a small integer ALU, called the S-unit, another controlled the floating-point adder, and another controlled the floating-point multiplier. So each instruction could direct *two* operations that were *directly usable* by the applications program, a floating-point add and a floating-point multiply. In comparison, a 360/85 or 370/168 or 3033: - didn't let the user program in horizontal microcode, even if it was writable, - had only *one* ALU for regular arithmetic, although there were supplementary ALUs for byte operations (also used for FP exponents) and address arithmetic Thus, while some horizontal microcode machines might be said to in some way be precursors of VLIW, it's a stretch. With the AP-120B, on the other hand, the resemblance is clear and unmistakable. Superficially, VLIW instructions are microcode-like. You direct the movement of data between functional units and internal registers. But VLIW presents multiple functional units, applicable to user problems, in a manner not useful for the microcoding of conventional instructions, so they _can_ be distinguished. The early articles about decoupled microarchitecture described the chips as going from CISC to RISC on the fly. Actually, what they did was closer to going from CISC to VLIW on the fly - since microinstructions were being composed, they could combine operations that belonged to two separate CISC instructions; this couldn't be done if you were just executing a microprogram, and that's why a 360/85 didn't split out ALU functions the way a CDC 6600 did. If it had, *then* its microcode could have been called a VLIW precursor with strong justification. (You could, theoretically, use the writable microcode store to code programs that did an EDMK and fixed-point arithmetic in parallel, though, which would be VLIW. Nobody ever _did_ that, though. Maybe it's a VLIW precursor only a patent lawyer could love.) John Savard |