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From: Alexei A. Frounze on 17 Aug 2007 05:38 On Aug 16, 2:37 pm, "Wolfgang Kern" <nowh...(a)never.at> wrote: > Matt asked: > > ... > > >> ;bits16 yet > >> 6a 20 push +20h > >> 1f pop ds > >> 66 67 a1 10 20 30 D8 mov eax,dword[D8302010h] > >> I use things like this very rare, as I need the opposite more often, > >> ie: calling true Realmode BIOS service from within PM32. > >> This needs a full back and forward switch (VM86 is just too slow for me). > > That's interesting. Are you saying that it is faster to switch back to > > true real mode than to switch to VM86, or that it is too slow to RUN in > > VM86? > > Yeah. I checked both and found that renounce of VM86 at all speeds up > everything against true RM linked BIOS-calls by a factor 15..30. > (one more time: "Sorry Alexei" VM86 is dead since long, at least for me). > > Ok, my OS and all 'my code' runs at PL=0, perhaps in any paranoid > protected environment like windoze/LinDoNix, a slow VM86-task may not > be recognised as a main time-eater anyway. Sorry, but I still have to see that myself and your words didn't convince me last time when we discussed this topic. From what you were saying I didn't see you were measuring the right times. I'm not saying you're right or wrong yet. I need to see it myself before I agree or disagree with you. It doesn't make much sense to me and I want to verify your assertions. Alex
From: Wolfgang Kern on 17 Aug 2007 06:11 Alexei A. Frounze wrote: >> this is why the GDT must be aligned to an 8 byte boundary. > Wrong, it must not (not in non-64-bit mode, at least). Mmh.. if I look at the IA32 GDTR/IDTR layout it is possible to have the tables at an odd address ... Have you ever tried it ? Wouldn't it slow down everything ? I always followed the recommendation of CPU manuals and align GDT/IDT to cache bounds. __ wolfgang
From: Wolfgang Kern on 17 Aug 2007 07:26 Alexei A. Frounze wrote: [about VM86 speed ...] >> Ok, my OS and all 'my code' runs at PL=0, perhaps in any paranoid >> protected environment like windoze/LinDoNix, a slow VM86-task may not >> be recognised as a main time-eater anyway. > Sorry, but I still have to see that myself and your words didn't > convince me last time when we discussed this topic. From what you were > saying I didn't see you were measuring the right times. I'm not saying > you're right or wrong yet. I need to see it myself before I agree or > disagree with you. It doesn't make much sense to me and I want to > verify your assertions. Right Alex, but if you check it within protected rings PL>0 then you may see VM86 faster than my method because of the RM<->PM32 links will take much more time then. __ wolfgang
From: Alexei A. Frounze on 17 Aug 2007 11:43 On Aug 17, 4:26 am, "Wolfgang Kern" <nowh...(a)never.at> wrote: > Alexei A. Frounze wrote: > > [about VM86 speed ...] > > >> Ok, my OS and all 'my code' runs at PL=0, perhaps in any paranoid > >> protected environment like windoze/LinDoNix, a slow VM86-task may not > >> be recognised as a main time-eater anyway. > > Sorry, but I still have to see that myself and your words didn't > > convince me last time when we discussed this topic. From what you were > > saying I didn't see you were measuring the right times. I'm not saying > > you're right or wrong yet. I need to see it myself before I agree or > > disagree with you. It doesn't make much sense to me and I want to > > verify your assertions. > > Right Alex, but if you check it within protected rings PL>0 then you > may see VM86 faster than my method because of the RM<->PM32 links > will take much more time then. I didn't get it. Can you elaborate? Alex
From: Alexei A. Frounze on 18 Aug 2007 03:25
On Aug 17, 3:11 am, "Wolfgang Kern" <nowh...(a)never.at> wrote: > Alexei A. Frounze wrote: > >> this is why the GDT must be aligned to an 8 byte boundary. > > Wrong, it must not (not in non-64-bit mode, at least). > > Mmh.. if I look at the IA32 GDTR/IDTR layout it is possible > to have the tables at an odd address ... > > Have you ever tried it ? Wouldn't it slow down everything ? > > I always followed the recommendation of CPU manuals and > align GDT/IDT to cache bounds. > > __ > wolfgang I have a number of apps that happen to have GDT at arbitrary offsets (multiple of 16, 2 and even odd). All worked. As for slowing down, once the segment descriptor's are cached in the CPU segment registers (their hidden parts). I wouldn't expect any noticeable slowdown. Alex |