where [BITS 32] directive?
in [ASM]
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From: James Harris on 15 Aug 2007 14:31 On 14 Aug, 19:18, "Bx.C / x87asm" <email.a...(a)is.invalid> wrote: .... > since the CPU is still in 16-bit mode until after the jump, the [bits 32] > should be placed between the jump and the clear_pipe label.... it is at this > point where the CPU is now in 32-bit mode since the segment descriptor gets > reloaded on the far jump... If the CPU were to take an interrupt between mov cr0,eax and jmp 08h:clear_pipe could it return from the interrupt already in Protected mode? In other words, does the mov cr0,eax actually set protected mode and the following jump just clear the prefetch queue. Or does the CPU remain in real mode until a far jump? If the former is the case then should interrupts be disabled over the transition to protected mode? -- James
From: James Harris on 15 Aug 2007 14:52 On 15 Aug, 19:31, James Harris <james.harri...(a)googlemail.com> wrote: > On 14 Aug, 19:18, "Bx.C / x87asm" <email.a...(a)is.invalid> wrote: > ... > > > since the CPU is still in 16-bit mode until after the jump, the [bits 32] > > should be placed between the jump and the clear_pipe label.... it is at this > > point where the CPU is now in 32-bit mode since the segment descriptor gets > > reloaded on the far jump... > > If the CPU were to take an interrupt between > > mov cr0,eax > > and > > jmp 08h:clear_pipe > > could it return from the interrupt already in Protected mode? In other > words, does the mov cr0,eax actually set protected mode and the > following jump just clear the prefetch queue. Or does the CPU remain > in real mode until a far jump? > > If the former is the case then should interrupts be disabled over the > transition to protected mode? I'll answer my own question with this extract I've found in the IA-32 Software Developer's Manual vol 3a 9.9.1 Switching to Protected Mode .... 1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI interrupts can be disabled with external circuitry. (Software must guarantee that no exceptions or interrupts are generated during the mode switching operation.) 2. Execute the LGDT instruction to load the GDTR register with the base address of the GDT. 3. Execute a MOV CR0 instruction that sets the PE flag (and optionally the PG flag) in control register CR0. 4. Immediately following the MOV CR0 instruction, execute a far JMP or far CALL instruction. (This operation is typically a far jump or call to the next instruction in the instruction stream.) 5. The JMP or CALL instruction immediately after the MOV CR0 instruction changes the flow of execution and serializes the processor. 6. If paging is enabled, the code for the MOV CR0 instruction and the JMP or CALL instruction must come from a page that is identity mapped (that is, the linear address before the jump is the same as the physical address after paging and protected mode is enabled). The target instruction for the JMP or CALL instruction does not need to be identity mapped. 7. If a local descriptor table is going to be used, execute the LLDT instruction to load the segment selector for the LDT in the LDTR register. 8. Execute the LTR instruction to load the task register with a segment selector to the initial protected-mode task or to a writable area of memory that can be used to store TSS information on a task switch. 9. After entering protected mode, the segment registers continue to hold the contents they had in real-address mode. The JMP or CALL instruction in step 4 resets the CS register. Perform one of the following operations to update the contents of the remaining segment registers. - Reload segment registers DS, SS, ES, FS, and GS. If the ES, FS, and/ or GS registers are not going to be used, load them with a null selector. - Perform a JMP or CALL instruction to a new task, which automatically resets the values of the segment registers and branches to a new code segment. 10. Execute the LIDT instruction to load the IDTR register with the address and limit of the protected-mode IDT. 11. Execute the STI instruction to enable maskable hardware interrupts and perform the necessary hardware operation to enable NMI interrupts. Random failures can occur if other instructions exist between steps 3 and 4 above. Failures will be readily seen in some situations, such as when instructions that reference memory are inserted between steps 3 and 4 while in system management mode.
From: Dirk Wolfgang Glomp on 15 Aug 2007 13:38 Am Tue, 14 Aug 2007 15:27:44 -0400 schrieb CodeMonk: > Frank Kotler wrote: >> Herbert Kleebauer wrote: >>> Frank Kotler wrote: >>> >>> >>>>>>>> And the >>>>>>>> monochrome screen is at B0000h, not B80000h, if you care... >>>>>>> >>>>>>> As far I remember, it's neither B0000h nor B80000. DOS programming >>>>>>> must be really dead when such essential values aren't correctly >>>>>>> remembered. >>>>>> >>>>>> Okay, refresh my memory... >>>>> >>>>> Both values contained an extra zero, but no big deal - it's like >>>>> 'mispelling' a word during an Instant Messaging session, they know what >>>>> you mean. >>>> >>>> If I'da meant "B000:0000" I would've said so. Are you guys telling me >>>> the tut is correct? >>> >>> >>> Isn't it b8000 for text mode (and a0000 for graphics mode)? >> >> For ega/cga/vga, yeah. For monochrome (ttl) cards, B0000h for text mode >> - mode 7, not mode 3 - and... ??? for graphics (no graphics at all on my >> old card). Newbie! :) >> >> Best, >> Frank >> > > For the *old* Hercules cards, both text and graphics mode memory began > at B0000h. No graphics on your card? That is fossil-like old. > > - Scott RBIL->Inter61a.zip->Interrup.a --------V-1000------------------------------- INT 10 - VIDEO - SET VIDEO MODE AH = 00h AL = desired video mode (see #00010) ..... (Table 00010) Values for video mode: text/ text pixel pixel colors disply scrn system grph resol box resolution pages addr 00h = T 40x25 8x8 320x200 16gray 8 B800 CGA,PCjr,Tandy ..... ..... ..... D0h = G . . 640x400 2 . B800 DEC VAXmate AT&T mode --------------------------------------------- Dirk
From: CodeMonk on 15 Aug 2007 17:17 Dirk Wolfgang Glomp wrote: > Am Tue, 14 Aug 2007 15:27:44 -0400 schrieb CodeMonk: > >> For the *old* Hercules cards, both text and graphics mode memory began >> at B0000h. No graphics on your card? That is fossil-like old. >> >> - Scott > > RBIL->Inter61a.zip->Interrup.a > > <snip> > Dirk Not sure if you're actually replying to me, but since you did: http://www.everything2.com/index.pl?node_id=1130121 - Scott
From: opexoc on 15 Aug 2007 17:44
On 14 Sie, 22:49, ope...(a)gmail.com wrote: > On 14 Sie, 21:54, Frank Kotler <fbkot...(a)verizon.net> wrote: > > > Google for "a20 - a pain from the past"... I'll save you the trouble: > > >http://www.win.tue.nl/~aeb/linux/kbd/A20.html > > Thanks for this link but I don't find there explanation why A20 line > is responsible for access odd megabytes. Sorry Frank. I have not noticed the connection beetwen bits in address line and "odd megabytes". Now I know that the answer was in this link. Wiktor |