From: luudee on 24 Mar 2010 08:16
On Mar 22, 1:31 am, Alessandro Basili <alessandro.bas...(a)cern.ch>
> On 3/20/2010 10:46 AM, HT-Lab wrote:
> > There are lots of places were you can legally download it from, if you do a
> > google search (amba bus protocol) then the first entry is wikipedia and the
> > second is:
> > If you read the second page it states:
> > Document confidentiality status
> > This document is Open Access. This document has no restriction on distribution.
> I just had a read to this document:http://www.opencores.org/downloads/soc_bus_comparison.pdf
> Apparently the wishbone seams much easier to use then the other two
> reported, but it seems to be it doesn't support address pipelining (as
> Rob already mentioned), which so far I don't have any element to
> evaluate whether this is a main problem or not.
> My main intent is to promote, or support and spread the concept of
> _reuse_ especially in the research world (where I belong to) where
> people are kind of keen to "reinvent" the wheel. I believe that a lot of
> efforts can be made more fruitful if a common interface would be available.
> Alessandro Basili
> CERN, PH/UGC
> Hardware Designer
The idea of using WISHBONE was two-fold:
1) It's simplicity and openness
2) If the OpenCores community would standardise on it, we could
develop "wrappers" or "bridges" to other buses, such as AHB and OPB
If you are developing an IP Core for deposit on OpenCores, it would
to use WISHBONE, if it will be technically feasible.
From: Alessandro Basili on 24 Mar 2010 15:58
> The idea of using WISHBONE was two-fold:
> 1) It's simplicity and openness
These were essentially the main characteristics that attracted me the
most, even though I still didn't understand how you handle two buses
with two different bus clocks, would you need a bridge between the two
or is it meant to be handled by two different bus controllers?
> 2) If the OpenCores community would standardise on it, we could
> develop "wrappers" or "bridges" to other buses, such as AHB and OPB
> for example.
I believe that wrappers or bridges will be needed only if the IP core
will be hierarchically below the wishbone interface. But as jt_eaton said:
> DO NOT create a wishbone interface and then place your core logic below it
> in the hierarchy. If you do and then later want to support a different bus
> then you are screwed. If you keep the wishbone in one module then it is
> alot easier to take that module and convert it into something like a AHB
and I tend to agree with his approach. In this case the IP core may have
several interfaces without the need of going through a wrapper or bridge.
> If you are developing an IP Core for deposit on OpenCores, it would
> make sense
> to use WISHBONE, if it will be technically feasible.
As far as I see it should not be so difficult and I agree that a more
widely use of this standard will help a lot. I believe that universities
and institutes should contribute to it the most since they are the more
in need of an open environment to fully contribute at any research level.
What I'm a bit skeptical about is that after almost 8 years since the
last revision there hasn't been much of a spread and I would like to
understand why and whether if there's something that "we", as a
community, need to do in order to boost it's usage.
From: Matthieu Michon on 25 Mar 2010 04:46
On Wed, 24 Mar 2010 20:58:15 +0100
Alessandro Basili <alessandro.basili(a)cern.ch> wrote:
> As far as I see it should not be so difficult and I agree that a more
> widely use of this standard will help a lot. I believe that universities
> and institutes should contribute to it the most since they are the more
> in need of an open environment to fully contribute at any research level.
> What I'm a bit skeptical about is that after almost 8 years since the
> last revision there hasn't been much of a spread and I would like to
> understand why and whether if there's something that "we", as a
> community, need to do in order to boost it's usage.
From where I stand, Wishbone and Avalon (used by Altera) buses aren't so different. IMO the lack of traction of the Wishbone bus can be explained by (amongst other things):
- No external devices (PHYs, memories, ...) supports Wishbone (I believe the chicken/egg issue is one the reasons). Looking at the number of open SPI/I2C/CAN cores around, such external devices would fuel the development of the Wishbone bus for sure (if the maker didn't go bankroupt yet).
- A lot of design units start "simple" (not even in a dedicated unit), where a simple dataflow I/F (data, strobe, ready/busy, request/grant, ...) would due the job. It's later that using a re-usable I/C bus is thought of.
These where my 2 cents.
Matthieu Michon <prenom.nom(a)gmail.com>