Computer Architecture
in [Hardware]
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Protecting 3x16 bits with 16 bits ? (crc8 + 8 bit hamming code seems perfect) Hello, I just had a better idea, since I forgot about the address check... Since a hamming code has a certain range I might as well use the full range to "ham" more bits ! ;) :) So there are 48 "gpu data bits" and the maximum addressing range is probably "16 bits" So that creates a total of: 48 true dat... 13 Feb 2010 23:47
Protecting 3x16 bits with 16 bits ? (crc8 + 7 bit hamming code?) Another interesting idea could be to do the following: Spent 8 bits on a crc8 for strong error detection. Spent 6 bits on a hamming code for 1-bit error correction. Spent 1 bit on hamming code extension for 2 bit error detection. Total of 15 bits used... one spare bit (?). This would probably create a very s... 13 Feb 2010 23:47
Draft paper submission deadline is extended: HPCS-10, Orlando, USA It would be highly appreciated if you could share this announcement with your colleagues, students and individuals whose research are in parallel computing, distributed systems, operating systems, computer architecture, grid-computing, VLSI, and related areas. Draft paper submission deadline is extended: HPCS-10... 13 Feb 2010 19:24
Protecting 3x16 bits with 16 bits ? (I wonder about LDPC codes for gpu ;)) I investigated hamming a bit and wondered what would happen if I left out 1 bit from all data bits in a parity calculation, all data bits would receive a parity bit... from that "experiment" it was pretty clear that this hamming idea can only correct single bit errors ?!? Well maybe not because the wikipedia li... 12 Feb 2010 23:32
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was: Notes on two presentations by Gordon Bell ca. 1998 Rick Jones <rick.jones2(a)hp.com> writes: Does it even have to be a "supercomputer" to look like a big multi-tiered switch? Is a Narus a supercomputer? HP/Convex has won a hard-fought competition to provide a 256-CPU, 184 GFLOPS Exemplar for a multi-year collaboration with CalTech and JPL. That's Calt... 11 Feb 2010 21:50
Protecting 3x16 bits with 16 bits ? (CRC16 on GPU ?! ;)) This page sounds good: http://www.ee.unb.ca/tervo/ee4253/crc.htm Lot's of 100% detection ! ;) This page explains how to do carryless arithmetic: http://www.repairfaq.org/filipg/LINK/F_crc_v32.html#CRCV_001 Now the question which remains is: How to do CRC16 with floating points on the gpu ? ;) :) By... 11 Feb 2010 17:18
Protecting 3x16 bits with 16 bits ? (crc16) Maybe this is a good solution, crc16: http://en.wikipedia.org/wiki/Cyclic_redundancy_check (math group included too, maybe it will get through ;)) Bye, Skybuck. "Skybuck Flying" <IntoTheFuture(a)hotmail.com> wrote in message news:6f76a$4b745dac$d53371df$29602(a)cache4.tilbu1.nb.home.nl... Hello, S... 11 Feb 2010 16:10
Protecting 3x16 bits with 16 bits ? (Raptor codes) This one is kinda interesting, raptor codes: http://tools.ietf.org/html/rfc5053 It seems to be something new... it seems to using some floating points and matrices... normally I don't like matrices but in this case I might make an exception since the gpu has support for it ;) But it seems to also use very ... 11 Feb 2010 16:10
Protecting 3x16 bits with 16 bits ? Hello, Soon I will attempt some gpgpu development/shader development... I have already done some tests and so forth the gpu and it's memory seem to be working just fine... (and fast ;) :)) No bit errors so far. However the thought of bit errors creeping into it is indeed a bit scary... The hardware is older... 20 Feb 2010 14:38 |