Computer Architecture

Need SimpleScalar GCC Compiler
My partner and I are doing a project involving SimpleScalar. We need to make a program of our own to use with sim-cache. I'm under the impression it's a simple matter of creating an executable with "ssbig-na-sstrix-gcc". However, I have no idea where to get this compiler. It's not in simplesim, simpletools, or ... 30 Nov 2006 13:41

Why so little parallelism?
Arbitrary vector permutation by a permutation vector, vector reversal, insertion of a vector into a vector, and so forth in log(n) time and O(n) switches if you allow pipelining is pretty obvious. Building on that, log(n) time sorting with O(n) elements with pipelining is pretty obvious. I just spent hours waiting ... 1 Feb 2007 06:47

Historical question, what went wrong with bubble memory?
kenney(a)cix.compulink.co.uk wrote: I can remember several years when magnetic bubble memory was going to be the next big thing, replacing most other forms of storage. It then seemed to disappear without trace. Has development stopped? Ken Young If I remember right it was very slow, very expensive... 20 Nov 2006 15:02

IA64 and emulator performance
Hi, I can't seem to find any (post-Montecito) numbers on IA64 and performance on 32-bit code. Does anybody know about relevant benchmarks or even approximate performance numbers? -k -- If I haven't seen further, it is by standing in the footprints of giants ... 8 Nov 2006 12:28

How Do You Schedule a Graphics Processor?
I like reading about how Folding(a)Home has a beta version that runs on a high-end ATI graphics processor (see http://techreport.com/etc/2006q4/gpu-folding/index.x?pg=1). Nice work. What I'm wondering about is how they manage to schedule the job(s) the run on the GPU so that they don't interfere with the regular ... 18 Oct 2006 05:45

Why magnetic drums was/are worse than disks ?
Sorry, what is the reason(s) that magnetic drums became worse than magnetic disks ? More bad surface shape for some technology processes, more low packaging density (in comparison w/disk packs having multiple plates) or something other ? Yours Mikhail Kuzminsky Zelinsky Institute of Organci Chemistry Mosco... 24 Oct 2006 23:16

Early dual processor chips?
I'm trying to find prior art wrt to a patent on single-chip designs which include more than one "processor" for a particular application. I appologize for not being able to be more specific here. I've been trying my luck with google groups here in c.a, but searching on "dual processor" tends to dig up dual proces... 24 Oct 2006 00:42

New information on POWER6
An EEtimes article <http://www.eetimes.com/showArticle.jhtml?articleID=193105767>, has the following information, not previously public (AFAIK): 1) L2 cache is 8 MB total (for the die presumably) 2) Memory bandwidth is 75Gbyte/second (for the die) 3) Minimum voltage for full operation (doing work) is 0.8V (f... 14 Oct 2006 04:13

speculative o-o-o execution of *special* instructions?
girish wrote: this is a basic doubt. on a processor that is .a superscalar .b with o-o-o execution .c multiple issue mechanism, what happens when the speculated path contains either (sure, even combination of) - .1 an instruction that can cause a software trap - like syscall in MIPS ... 24 Oct 2006 23:47

Ultra simple computing
.... "ultra simple computing". Computers are currently too complicated - they crash regularly, are expensive, and have security risks, but it doesn't all have to be so complex. Computers can be redesigned from the ground up with tens of thousands of little chips to distribute the load. It will mean there will... 15 Oct 2006 16:26