How Many Processor Cores Are Enough?
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From: Nick Maclaren on 18 Oct 2006 11:14 In article <1161182868.998560.165020(a)m7g2000cwm.googlegroups.com>, "girish" <girishvg(a)gmail.com> writes: |> |> > |> > As I said, look up RC delay. Until and unless someone can get |> > |> > opto-electronics working for internal chip 'wiring', that will be |> > |> |> > |> correct me if i am wrong. but is this referring to -- wire-less chip |> > |> interconnect or optical chip interconnect? |> > |> > No. As I said, look it up. It will explain many of the replies from |> > other people. |> thanks. |> |> let me understand this. (been some time i studied this). are we talking |> about - |> R |> -------------wwwwww-------------------------------- |> | |> C | |> ======= |> ======= |> | |> | |> ------------------------------------------------------------ Yes. Regards, Nick Maclaren.
From: Tim McCaffrey on 18 Oct 2006 11:45 In article <1161088788.071516.69900(a)f16g2000cwb.googlegroups.com>, already5chosen(a)yahoo.com says... > >I would like to see an example of microarchitectural change in >processors from the following list (PIII, K7, K8, P4, PM, Merom) that >broke working PII application program, library, device driver or any >other SW component that was written with full conformance to PII >variant of IA-32 architecture. Well, I can't give you a PII example (why PII?), but there is an interesting example from the 8086->286 (I think, or was it 486...?). Anyway, many I/O devices couldn't handle back to back I/Os, and instead of putting in the extra hardware to fix this, the programmer was obligated to make sure there was enough delay between to I/O instructions to a device to let it recover. Originally, the Intel documentation said to insert a JMP $+2 (jump to next instruction) to flush the prefetch pipeline and cause a few memory cycles between the I/O instructions. By the time of the 486 (and possibly the 286?), this didn't work anymore, both because the processor was clocked faster, and because of the cache (I know the 286 didn't have cache, but it had a faster bus, faster clock, and executed instructions quicker). Anyway, the next solution was to do an I/O to device address 0, which didn't exist on any PC (probably due to pure luck), which force an I/O cycle, which allowed enough delay to take place. On today's PC, I'm not sure an OUT to address 0 would work ok (I guess it goes to the legacy chip, which probably tosses it?), on the other hand, everything is PCI, and PCI doesn't require software timed delays.... Today, I suspect if there any problems, it is in the changes in relative execution time that cause problems. E.g. the interrupt latency for a P4 is far worse than a PIII. Also, things like prefetching, branch prediction, etc, can change an optimization in one generation to be a pessimization in the next. - Tim
From: rohit.nadig@gmail.com on 19 Oct 2006 01:46 Dennis, The use of such profanity is unnecessary and immature. I was not in the least being disrespectful to you (or to Architects/Micro-architects). Maybe I was wrong in trying to mediate, but you could have said so, and I would have listened to you. So, what would you do if I were standing in front of you? Punch me in the nose and get arrested like it were a brawl in a cheap college bar? -Rohit > >> Then shut the f*ck up. There's enough noise on USENET > >> already without ever pissant Gmail user puking up onto > >> a thread just to tell everyone they don't care about it.
From: Dennis M. O'Connor on 19 Oct 2006 02:45 <rohit.nadig(a)gmail.com> wrote ... >> >> Then shut the f*ck up. There's enough noise on USENET >> >> already without ever pissant Gmail user puking up onto >> >> a thread just to tell everyone they don't care about it. > > The use of such profanity is unnecessary and immature. Bullshit. Profanity is the red hot chili pepper of language. Used properly, it enhances. Overused, it interferes. And technically, I didn't use any profanity. :-P > I was not in the least being disrespectful to you > (or to Architects/Micro-architects). What you were being, and are being, is useless non-contributing noise. Go find a USENET-for-newbies FAQ and read it. -- Dennis M. O'Connor dmoc(a)primenet.com
From: ranjit_mathews@yahoo.com on 19 Oct 2006 10:20
Joe Seigh wrote: > Nick Maclaren wrote: > > > > Much of the load/store atomicity is unspecified, especially with regard > > to multiple cores and data objects which need a lower alignment than > > their size. That is a common source of problem. Not having a standard way to specify that one wants a given data object to be given an alignment at least equal to its size is also a source of problems. > Case in point, the complete and utter lack of a clear and unambiguous > publically documented memory model for Intel architecture. We've > had comments from Andy Glew to that effect here on c.a. > > Joe Seigh > > When you get lemons, you make lemonade. > When you get hardware, you make software. |