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Big OOO, SpMT, and possible designs (Was Re: Free/Open x86 Sim)
Hello all, "Andy 'Krazy' Glew" <ag-news(a)patten-glew.net> wrote in message news:4BE72955.9000809(a)patten-glew.net... On 1/25/2010 3:43 AM, nedbrek wrote: Hello all, "Andy "Krazy" Glew"<ag-news(a)patten-glew.net> wrote in message news:4B5C999C.9060301(a)patten-glew.net... nedbrek wrote: Tha... 1 Jun 2010 07:32
A post to comp.risks that everyone on comp.arch should read
http://catless.ncl.ac.uk/Risks/26.06.html#subj12 I'd recommend it to every technical weenie posting to comp.*, but I regard the situation as essentially hopeless. <quote> This despite the fact that many nasty things were said about Dijkstra, such as "ivory tower theorist"; for in fact, "speaking truth to [g... 15 May 2010 11:30
polling / interrupt
Hello, It seems that polling is the "dirty" way of using a device, whereas interrupt is the prefered one, but that one implies some context switching delays. Are there still devices today on which polling is used (I think of keyboard and mouse, but I'm not sure) ? Are the both techniques used on some devi... 8 Jun 2010 14:50
Nvidia Secret Sauce for ECC?
http://www.anandtech.com/show/2977/nvidia-s-geforce-gtx-480-and-gtx-470-6-months-late-was-it-worth-the-wait-/4 See http://semipublic.comp-arch.net/wiki/Poor_Man%27s_ECC In particular US patent 7,117,421, Transparent error correction code memory system and method, Danilak, assigned to Nvidia, 2002. http://s... 11 May 2010 02:26
Free/Open x86 Sim (was Re: Multi-star)
On 1/25/2010 3:43 AM, nedbrek wrote: Hello all, "Andy "Krazy" Glew"<ag-news(a)patten-glew.net> wrote in message news:4B5C999C.9060301(a)patten-glew.net... nedbrek wrote: That's where my mind starts to boggle. I would need see branch predictor and serialization data showing a window this big woul... 9 May 2010 17:35
x86 i/o management
Hello, It seems that x86 architecture manages i/o communication through i/o ports as well as memory-mapped i/o (refering to the content of /proc/ iomem and /proc/ioports on my OS). Is the Intel management of both types of i/o communication just due to historical constraints (and i/o ports management is just ... 13 May 2010 19:21
Intel cache inclusion
Hello, Does anyone know the history of cache inclusion on Intel processors? Last I'd paid attention, Intel had no plans for having strict inclusion of the cache hierarchy. I know that in the late 90s Intel used what they called “convenient inclusion,” that is the last level of cache was neither fully exclusive ... 7 May 2010 11:07
Ye Olde Log-Based SpMT Uarch
> On Mon, 26 Apr 2010 19:38:01 -0700, "Andy "Krazy" Glew" <ag-news(a)patten-glew.net> wrote: I'll do a separate followup post, with the (vain) attempt to change the topic. I don't think I have ever described my SpMT ideas to this newsgroup. Nothing proprietary, just the by now really old stuff that I worked on... 5 May 2010 21:35
Processors stall on OLTP workloads about half the time--almostno matter what you do
Quadibloc wrote: On Apr 30, 5:57 am, Anne & Lynn Wheeler <l...(a)garlic.com> wrote: from above (2006) article: is that the price per MIPS today is approximately six times higher than the $165 per MIPS that the traditional technology/price decline link would have produced Part of this is ... 3 May 2010 19:48
Life After Moore's Law
This article on Forbes.com http://www.forbes.com/2010/04/29/moores-law-computing-processing-opinions-contributors-bill-dally.html came to my attention from visiting HPC Wire. I think that he is right that massively parallel chips, designed to maximize throughput per transistor, are more useful for problems th... 4 May 2010 06:47
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