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"SIE" on a RISC architecture
I was reading about the IBM SIE instruction on Andy's wiki (Article at ), and a few things struck me. The first is the question of "If I'm implementing this efficient virtual machine system, do I really need a separate 'user mode'?". The second is "How can this instruct... 14 Jul 2010 13:10
A naive conjecture about computer architecture and artificial intelligence
In article <8c504e90-cc74-4c15-bd14-63f0c1be7fb2(a)>, MitchAlsup(a) says... Call Indirect and Jump Indirect Tables with and without hashing are generally pretty good given suficient area to contain the footprint and a little cleverness of the designers tuning the hash. Here, I... 8 Jul 2010 14:42
Opcode Parsing & Invalid Opcodes
Nimai wrote: I'm learning to program in straight machine code, and I just finished reading the Intel manuals. I have a burning question that the books haven't answered, maybe I'm just stupid and I missed it. If I do a JMP to a bunch of garbled data, how does the prefetching process know where ... 6 Jul 2010 20:01
Cache line list handling
Hi Just wondered how useful this idea maybe. 64 bytes => 16 * 32 bit values = 4 nodes. Node ==== 0. chain pointer 1. value 2. reference count 3. moved to please update pointer The general idea is to migrate any referenced cell into the referencing cache line or a closer one off the free list. Thi... 16 Jul 2010 18:45
2nd call - Applied Computing 2010: until 26 July 2010
Apologies for cross-postings. Please send to interested colleagues and students -- CALL FOR PAPERS - Deadline for submissions (2nd call): 26 July 2010 -- IADIS INTERNATIONAL CONFERENCE APPLIED COMPUTING 2010 October 14 - 16, 2010 – TIMISOARA, ROMANIA ( * Conference backgro... 5 Jul 2010 07:46
A naive conjecture about computer architecture and artificialintelligence
Robert Myers wrote: My if-it-worked-more-than-once-it-will-probably-work-again machinery thinks it sees a pattern: 1. Anticipation is central to (almost) all cognitive and computational processes. Anticipation, afaik, is just another name for prediction, right? Pretty much all current computers (wi... 13 Jul 2010 08:41
A naive conjecture about computer architecture and artificial intelligence
I am struck by the success of a relatively clueless strategy in computer microarchitecture: If it worked more than once, it will probably work again. The only possible improvement is to learn to anticipate exceptions. I'd call that bottom up prediction. Most top-down prediction schemes (I think I understa... 14 Jul 2010 10:56
Lolling at programmers, how many ways are there to create a bitmask ? ;) :)
Seebs wrote: On 2010-05-27, Skybuck Flying <IntoTheFuture(a)> wrote: Question is what happens when "shl 32" is done. sigh According to the intel manual the result would be undefined ?!? Yes. Does that mean the result could be garbage ??? Tell you what. Try post... 29 Jun 2010 17:22
x86 simulator (Was Re: RISC load-store verses x86 Add from memory.)
Hello all, "Andy 'Krazy' Glew" <ag-news(a)> wrote in message news:4C2627FD.9030100(a) On 6/25/2010 5:51 PM, mac wrote: The Pin interface,, may be a good start. I meant to post a status update on my search for x86 performance simulators... I look... 2 Jul 2010 10:10
Picking N-th ready element (e.g. in an OOO scheduler) One common operation in schedulers is picking the 1st, or 1st and 2nd, or ... N-th ... ready elements to schedule. Without loss of generality we will assume that we are picking in a physical order. E.g. we assume that an array looks like 0 1 ... 21 Jul 2010 09:07
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