Computer Architecture
in [Hardware]
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Micro Men on BBC4 today 22:30 "Urs" <sinclairql25(a)gmail.com> wrote in message news:95815f7d-1045-4af5-8f5b-ff0fc0dde698(a)40g2000vbr.googlegroups.com... Hi all Micro Men - the battle between Clive Sinclair and Chris Curry for the 1980s home computer market - is being broadcasted again today at 22:30 on BBC4. http://www.bbc.co.uk/p... 23 May 2010 07:03
RLE acceleration hardware for nextgen graphics ?! ;) :) Hello, Last time I saw/heared/read John Carmack (the famous programmer of Doom and Quake) talking about nextgen graphics rendering technology he showed a demo of "voxel/volume" based rendering. Such voxel's/volume's based rendering would probably need special hardware to quickly compresses and decompress vo... 26 May 2010 19:09
FAKE CONFERENCE 2nd call - INFORMATICS 2010: submissions until 31 May 2010 >-- CALL FOR PAPERS - Deadline for submissions (2nd call): 31 May 2010 -- IADIS INTERNATIONAL CONFERENCE INFORMATICS 2010 Freiburg, Germany, 26 � 28 July 2010 (http://www.informatics-conf.org/) part of the IADIS Multi Conference on Computer Science and Information Systems (MCCSIS 2010) Oh, look, it's ... 20 May 2010 14:58
2nd call - INFORMATICS 2010: submissions until 31 May 2010 Apologies for cross-postings. Please send to interested colleagues and students -- CALL FOR PAPERS - Deadline for submissions (2nd call): 31 May 2010 -- IADIS INTERNATIONAL CONFERENCE INFORMATICS 2010 Freiburg, Germany, 26 28 July 2010 (http://www.informatics-conf.org/) part of the IADIS Multi Conference o... 20 May 2010 13:51
1 lane, 2 lane, 3 lane processor cost ? Hello, x86 has usually two operands/parameters like so: mov a, b Why not three ? Why not one ? Maybe it's because multiple lanes would make the processor more costly ? Does the opposite apply as well ? For example a processor could be designed with just one lane to memory which would work as follows... 20 May 2010 16:05
Brain teaser: Can RLE compression work for interleaving streams ? For example R,G,B streams ?! Say the input stream is as follows: R,G,B, R,G,B, R,G,B, R,G,B, R,G,B, R,G,B Compression: RLE for R ? RLE for G ? RLE for B ? The mission is to output it again as follows: R,G,B, R,G,B, R,G,B, R,G,B, R,G,B, R,G,B Do you believe RLE compression is possible for interleaved streams ? ;) If you do be... 21 May 2010 08:23
No lock for bt instruction ? Hello, The intel manual "The IA-32 Intel Architecture Software Developer's Manual, Volume 2A, Instruction Set Reference, A-M, Document Number 253666 rev 19.pdf" mentions LOCK prefix is available for the BTC, BTR, BTS instructions but it doesn't mention it for BT instruction ?!? Is this correct ? Is there... 19 May 2010 14:52
Big OOO, SpMT, and possible designs "nedbrek" <nedbrek(a)yahoo.com> writes: The ironic thing, (which we demonstrated, and which made us hugely unpopular) is that massive many-core burns just as much (or more) power than a smart OOO on anything but grossly parallel applications. That is assuming you are actually powering those that you don... 4 Jun 2010 08:05
FAKE CONFERENCE Call for papers : HPCS-10, USA, July 2010 If you want a conference where they accept any paper if you pay the application fee, and there's plenty of time to take the family to Disney World since nobody but the authors goes to the sessions, you'll enjoy this conference. If you want one where the papers have competent peer review and the attendees are wor... 16 May 2010 11:19
Call for papers : HPCS-10, USA, July 2010 It would be highly appreciated if you could share this announcement with your colleagues, students and individuals whose research are in parallel computing, distributed systems, operating systems, computer architecture, grid-computing, VLSI, and related areas. Call for papers : HPCS-10, USA, July 2010 The 201... 16 May 2010 09:09 |