First  |  Prev |  Next  |  Last
Pages: 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Energy usage per application ?
Hello, Here is a whacky idea: Would it be possible to measure the energy usage per application ? So that a user could easily see it... like the windowss' task manager ? Bye, Skybuck. ... 13 Apr 2010 21:48
Faster image rotation
[ NB: CROSS-POSTED to comp.arch, comp.arch.embedded, comp.programming ] [ Followup-To: set to comp.programming ] Hello, I imagine the following problem has been efficiently solved over a million times in the past. I need to rotate a picture clockwise 90 degrees. Conceptually, my picture is represented by ... 26 Apr 2010 18:19
Which is the most beautiful and memorable hardware structure in a ?CPU?
In comp.arch.fpga MitchAlsup <MitchAlsup(a)aol.com> wrote: (snip) It was not so much that I was concentratng on Linpack, We (shebanow and I) were trying to build a machine that could perform as if it were a vector machine on vectorizable codes (without vector instructions:: i.e. native 88100 instructions ... 5 Apr 2010 14:57
Are the x86 transcendental functions broken by design?
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43599 They claim that "fsin/fcos are known to get wrong results for certain values and their precision is nowhere near acceptable". Put aside the range reduction process, mentioned in the manual, what else is known about their alleged lack of accuracy? I always thoug... 2 Apr 2010 21:28
Intel to sell processor which is 1000x faster than anything ever seen before !
Needless to say .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 1 April fools ! =D (Intel would never do such a thing, they scared to loose to many sale... 31 Mar 2010 19:55
Comparing GPUs array processor architectures: AMD vs. Nvidia vs.Intel
We (comp.arch) have discussed how I perceive the "SIMD" GPU architectures to be truly SIMT, as Nvidia has coined the term. Or "coherent threaded" or NIMT, in my terminology. Now let's talk about the microarchitectures of the shader processors. Nvidia's shaders are apparently strictly scalar. Intel's seem to... 31 Mar 2010 02:12
Which is the most beautiful and memorable hardware structurein a CPU?
The two hardware datastructures supporting out of order execution: Reservation stations. And, less beautifully, the register renaming map. But then I am biased. -- Really, I do think that the reservation stations are beautiful. Even the naive CAM implementation. Especially since there are more effici... 3 Apr 2010 13:42
Which is the most beautiful and memorable hardware structure in a CPU?
In article <hosgq9$h5m$1(a)smaug.linux.pwf.cam.ac.uk>, nmm1(a)cam.ac.uk says... In article <27ebdb37-e3ba-4559-be7d-d7f3b6613d77(a)30g2000yqi.googlegroups.com>, MitchAlsup <MitchAlsup(a)aol.com> wrote: The most memorable hardware structure is the vector indirect addressing mode. Yes. There were and are mo... 30 Mar 2010 13:51
Which is the most beautiful and memorable hardware structure in a CPU?
On Mon, 29 Mar 2010 08:26:25 -0700 (PDT), jacko <jackokring(a)gmail.com> wrote: I think it was a high level language feature first. Are you talking of indexed indirect addressing mode (reg+#immediate) or the link unlink instruction sets for setting the stack pointer? Would the 6502 8 bit micro (ZZ),Y mode c... 2 Apr 2010 00:38
FITS due to certain block
hello. our hardware team seems to have almost concluded that the TLBs are the primary culprit. the countermeasure(s) such as parity bit, will for sure lead to cut down on some other feature, to balance the die size and all that. impacting software/kernel to some extent. please help me understand - why TLBs? is thi... 31 Mar 2010 06:31
First  |  Prev |  Next  |  Last
Pages: 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26