FPGA -> SATA?
in [FPGA]
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From: fpga_toys on 27 Aug 2006 15:38 fpga_toys(a)yahoo.com wrote: > and to make sure the documentation > for these boards is complete, including the compliance failures. This is probably the most unethical part of Xilinx, ommissions which suck you and I into wasting valuable time and resources on a completely unusable design strategy. How do you trust anything, when your supplier has a track record of omissions ... and failure to disclose problem areas .... from valid (meets ISE timing reports) designs failing on parts, to lack of SATA compliance of reference designs?? And then compound that with Austin's and Peter's overt denial of problems in this forum, till cornered. "Lost, Totally" (as Austin ridicules) .... is Xilinx, Austin, and Peter.
From: fpga_toys on 27 Aug 2006 15:46 Martin E. wrote: > I am looking for a way to read/write to a SATA drive from an FPGA. I've > looked around. Nothing seems to fit the bill. Any ideas worth considering? Hi Martin ... would like to share an email reply I got from someone who seems to be a bit gunshy about publicly suggesting Altera: "there is not much for Altera to listen too, SATA defenetly works on Altera when using SAPIS PHY. in the regards of making S-3GX serdes directly SATA compliant, sure Altera does it if it technically reasonable. There is no need for Altera to license something. Its just the serdes-pll block characteriscitcs, either they are flexible enough to be use in SATA compliant mode or not." Something I will certainly be looking into this week. It would be nice if the Altera folks would confirm this specifically, and offer some public confirmation as there seems to be several of us with potential near term design wins for Altera if true.
From: Antti Lukats on 27 Aug 2006 16:29 "Falk Brunner" <Falk.Brunner(a)gmx.de> schrieb im Newsbeitrag news:4ldt6eF1f1g8U1(a)individual.net... > Antti Lukats schrieb: > >> there is still a possibility to get V4FX or V5xxT MGTs to work with SATA >> gen 1 - the RX and TX MGTs are configured with 4 to 1 datawidht ratio and >> same ref clock, the RX is configured as full bypass with clock >> permanently disabled (V4 MGT new feature) . Those the RX would be running >> at at 6GBit/s, the RX CDR and PCS functions would have to be implemented >> in FPGA fabric. Not an easy task but doable. > > Hmm, maybe. But probably with a hell of logic ressources. If it would be > easy, Xilinx would have implemented it into the hard macro, right? > But I guess the world (of SATA) is not that bad. AFAIK the spread > sprectrum clocking in OPTIONAL and is activated by a register in the > drive. So the FPGA application can run fine without spread spectrum option > (ok, a metal case will help to fight EMC problems) > No big deal at all for me. > Comming generations of FPGAs will support spread spectrum stuff. > > Regards > Falk Hi Falk, hmm.. I havent checked that, I actually also assumed that spread spectrum is optional, but I did not check on the spec. So I commented biased on Xilinx assumptions that the spread spectrum clock makes some drivers not useable. Last time I worked with Xilinx SATA I wasnt as far as about to worry about spread spectrum. V2Pro was clearly out SATA of spec because CDR hard lock range as there was no cure to that. This is clearly fixed in V4FX - well maybe we should wait up SEG's comments on this. Antti
From: Antti on 27 Aug 2006 16:33 fpga_toys(a)yahoo.com schrieb: > Martin E. wrote: > > I am looking for a way to read/write to a SATA drive from an FPGA. I've > > looked around. Nothing seems to fit the bill. Any ideas worth considering? > > Hi Martin ... would like to share an email reply I got from someone who > seems to be a bit gunshy about publicly suggesting Altera: > > "there is not much for Altera to listen too, SATA defenetly works on > Altera when using SAPIS PHY. in the regards of making S-3GX serdes > directly SATA compliant, sure Altera does it if it technically > reasonable. There is no need for Altera to license something. Its just > the serdes-pll block characteriscitcs, either they are flexible enough > to be use in SATA compliant mode or not." > > Something I will certainly be looking into this week. It would be nice > if the Altera folks would confirm this specifically, and offer some > public confirmation as there seems to be several of us with potential > near term design wins for Altera if true. gosh - there is an overview document at Altera website with Nuvation SATA IP core working in Altera FPGA - uses external SAPIS compliant PHY. http://www.nuvation.com/ipcores/sataa.html above is the nuvation link Antti
From: Antti on 28 Aug 2006 02:00
fpga_toys(a)yahoo.com schrieb: > fpga_toys(a)yahoo.com wrote: > > and to make sure the documentation > > for these boards is complete, including the compliance failures. > > This is probably the most unethical part of Xilinx, ommissions which > suck you and I into wasting valuable time and resources on a completely > unusable design strategy. > > How do you trust anything, when your supplier has a track record of > omissions ... and failure to disclose problem areas .... from valid > (meets ISE timing reports) designs failing on parts, to lack of SATA > compliance of reference designs?? And then compound that with Austin's > and Peter's overt denial of problems in this forum, till cornered. > > "Lost, Totally" (as Austin ridicules) .... is Xilinx, Austin, and Peter. eeaaasy up! 1) XUP Board is *not* made by Xilinx, neither is Xilinx claiming it can do SATA 2) At the time SEG designed ML300 V2Pro MGT characterization was possible not completed and/or SEG had no information on the actual useability of SATA on V2Pro. So the only thing to be fixed is one line in ML300 documentation, I think most other Xilinx own referencies to V2Pro-SATA have been fixed. One documentation item not being fixed can be 'just overlooked' by someone. 3) ML405 and ML410 also include SATA - on those boards I would assume it should be useable. However it is also remotly possible they got designed when the FX silicon was not tested as the V4FX MGT testing was finished very late. in any case - I can not and do not want to belive that Xilinx designed boards with features knowing not to work (at the time of the board design). Antti |