FPGA -> SATA?
in [FPGA]
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From: fpga_toys on 28 Aug 2006 20:34 Austin Lesea wrote: > As for the future, I have said that we are not SATA compatible now, and > have no IP today, and that is true. Then completely update the docs online to be specifically clear. Not hidden 67 pages in, a non-descript area, roughly fine print.
From: fpga_toys on 28 Aug 2006 20:35 fpga_t...(a)yahoo.com wrote: > Austin Lesea wrote: > > As for the future, I have said that we are not SATA compatible now, and > > have no IP today, and that is true. > > Then completely update the docs online to be specifically clear. Not > hidden 67 pages in, a non-descript area, roughly fine print. Beter yet, revise to docs to not call it SATA, but rather a Xilinx bit serial development prototype for testing protocols such as SATA.
From: Phil James-Roxby on 29 Aug 2006 10:42 fpga_toys(a)yahoo.com wrote: > Antti wrote: > >>1) XUP Board is *not* made by Xilinx, neither is Xilinx claiming it can >>do SATA > > > 1) title blocks on schematics ... Xilinx authorship/ownership > 2) Reference manual ... Xilinx authorship/ownership > 3) PCB artwork ... Xilinx authorship/ownership > 4) Search RM for Digilent ... reference only compatability with > Digilent boards. > > The unit does have Digilent compatable I/O ports, and may well have > been designed under contract for Xilinx, but that does make it a Xilinx > labeled Product that they claim ownership of, no matter who is building > it for them. In fact, everything suggests it's actually a Xilinx > Research Labs design instead ... specifically using Digilent I/O > connectors for the University Program, to make it compatable with > student board projects. > > And yes, I did finally find the statement on the bottom of page 67 in > the reference manual which starts "the SATA specification requires an > out of band signalling state that is to be used when the channel is > idle. ... " > > Which means that since this is REQUIRED, and not provided the serial > interfaces are NOT SATA, but simply have the same data rates and > encoding ... not SATA which is a full system level specification. Using > SATA everywhere to describe the interface, and not meeting the > specification is simply bait and switch, substituting the Xilinx bit > serial interconnect in it's place which just happens to be a > non-compatable subset of the SATA standard. > > A parallel 16 bit data bus with control signals is not SCSI, unless it > at least is capable of operating with the complete SCSI protocol ... > anything short of that, and it's SASI, Pertec, or some other 16 bit > bus, maybe even 16 bit ISA/EISA. > fpga_toys, The reason why SATA connectors are used in the XUP board is primarily to provide inexpensive high-speed connection between boards, either between 2 boards, or a number of boards in a ring. As the SATA leads are a commodity item, they are really inexpensive compared to other high-speed leads, and easy to get hold of around the world. That said, its understandable that people see SATA and immediately think hard drives. We tried in the documentation to explain the difficulty of connecting to drives, for example, on page 67 of the user guide, we stated The SATA specification requires an out-of band signalling state that is to be used when the channel is idle. This capability is not directly provided by the MGTs. Two resistors, an FET transistor, and two AC coupling capacitors along with special idle state control signals add the out-of-band IDLE state signaling capability to the MTGs. Additional off-board hardware can be required to properly interface to generic SATA disk drives. I know this doesn't help your particular situation - you still have a very nice board, even if it doesn't work for your SATA project. Please drop me a line if you'd like to discuss this further - I'd be particularly interested in any thoughts you have on how we could have documented this better. Phil
From: Antti on 29 Aug 2006 11:04 Phil James-Roxby schrieb: > fpga_toys(a)yahoo.com wrote: > > Antti wrote: > > > >>1) XUP Board is *not* made by Xilinx, neither is Xilinx claiming it can > >>do SATA > > > > > > 1) title blocks on schematics ... Xilinx authorship/ownership > > 2) Reference manual ... Xilinx authorship/ownership > > 3) PCB artwork ... Xilinx authorship/ownership > > 4) Search RM for Digilent ... reference only compatability with > > Digilent boards. > > > > The unit does have Digilent compatable I/O ports, and may well have > > been designed under contract for Xilinx, but that does make it a Xilinx > > labeled Product that they claim ownership of, no matter who is building > > it for them. In fact, everything suggests it's actually a Xilinx > > Research Labs design instead ... specifically using Digilent I/O > > connectors for the University Program, to make it compatable with > > student board projects. > > > > And yes, I did finally find the statement on the bottom of page 67 in > > the reference manual which starts "the SATA specification requires an > > out of band signalling state that is to be used when the channel is > > idle. ... " > > > > Which means that since this is REQUIRED, and not provided the serial > > interfaces are NOT SATA, but simply have the same data rates and > > encoding ... not SATA which is a full system level specification. Using > > SATA everywhere to describe the interface, and not meeting the > > specification is simply bait and switch, substituting the Xilinx bit > > serial interconnect in it's place which just happens to be a > > non-compatable subset of the SATA standard. > > > > A parallel 16 bit data bus with control signals is not SCSI, unless it > > at least is capable of operating with the complete SCSI protocol ... > > anything short of that, and it's SASI, Pertec, or some other 16 bit > > bus, maybe even 16 bit ISA/EISA. > > > > fpga_toys, > > The reason why SATA connectors are used in the XUP board is primarily to > provide inexpensive high-speed connection between boards, either between > 2 boards, or a number of boards in a ring. As the SATA leads are a > commodity item, they are really inexpensive compared to other high-speed > leads, and easy to get hold of around the world. > > That said, its understandable that people see SATA and immediately think > hard drives. We tried in the documentation to explain the difficulty > of connecting to drives, for example, on page 67 of the user guide, we > stated > > The SATA specification requires an out-of band signalling state that is > to be used when the channel is idle. This capability is not directly > provided by the MGTs. Two resistors, an FET transistor, and two AC > coupling capacitors along with special idle state control signals add > the out-of-band IDLE state signaling capability to the MTGs. Additional > off-board hardware can be required to properly interface to generic SATA > disk drives. > > I know this doesn't help your particular situation - you still have a > very nice board, even if it doesn't work for your SATA project. Please > drop me a line if you'd like to discuss this further - I'd be > particularly interested in any thoughts you have on how we could have > documented this better. > > Phil Phil, the OOB workaround is on board. that fine, so basically it useable for SATA (if you are lucky and the drive is working in suitable for V2Pro manner) but there is NO off-board hardware available that would connect to the SATA connector of XUP board and make the XUP to fully work with any generic SATA drive. Correct me if I am wrong about this. there are many choices to make XUP board a SATA board 1) use add-on board with SATA PHY 2) use add-on board with SATA PATA bridge 3) use add-on board with PCI-SATA bridge 4) use add-on board with some other SATA bridge but none of those solutions would use the SATA connectors that are on board. sure SATA connectors are nice low cost connectors suitable for high speed transmittion, but if SATA connectors are added to any board for other intended use then SATA then this should be fully described and explained in the board documentation, what currently isnt the case. latest manuals for at least, those boards ML300 XUP V2Pro ML405 ML410 all list that SATA is operational and useable, not stating that there are severe restrictions regarding the possible use, and that there are no workarounds available. So all those documents should list something like: SATA connectors can be used for custom protocols, and for SATA experiments with the SATA products that do not use spread spectrum. additionally ML300 and XUP board documentation should read: can only work with SATA drivers when the SATA drive bit clock initial error is less than +-150ppm (SATA spec is +-300ppm) additionally ML300 documentation should read: for SATA OOB signalling external add on circuitry is required. without those additions to the manuals, some p***** off guy could get some lawer and sue Xilinx on false advertizing. I guess no one is so upset, and it would not pay off, but it would still nice to be clean as of not adertizing features that either can not be used, or can only be used with severe restrictions Antti
From: fpga_toys on 29 Aug 2006 19:34
Phil James-Roxby wrote: > That said, its understandable that people see SATA and immediately think > hard drives. We tried in the documentation to explain the difficulty > of connecting to drives, for example, on page 67 of the user guide, we > stated Hi Phil, People have a right to get upset when you advertise/describe one thing, and deliver something completely different. Consider selling 74LS02 chips and calling them PLD's or FPGA's. Sure, you have a fine bit serial prototype bench, SATA shouldn't be anywhere in ANY document unless it's standard conforming product. |