How Many Processor Cores Are Enough?
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From: Bill Todd on 28 Sep 2006 20:03 Tommy Thorn wrote: > Bill Todd wrote: >> Well, since IIRC the processing cores are running at a princely 1.91 MHz > > Well, you recall incorrectly. It's 3 GHz, cf. > http://www.tomshardware.com/2006/09/27/idf_fall_2006/page2.html You really need to work on your reading comprehension: there is nothing on the page that you cite above that remotely suggests that the prototype runs at 3 GHz (the only mention of that clock rate is in reference to a current P4's FP performance). The reference that gives the 1.91 MHz figure is http://www.theinquirer.net/default.aspx?article=34623 - bill
From: Bill Todd on 28 Sep 2006 20:11 Joe Seigh wrote: > Nick Maclaren wrote: >> In article <srKdnUtcqoTDaIbYnZ2dnUVZ_rCdnZ2d(a)comcast.com>, >> Joe Seigh <jseigh_01(a)xemaps.com> writes: >> |> Terje Mathisen wrote: >> |> > |> > You still need some what to handle async inter-core >> communication! I.e. |> > I believe that you really don't have any >> choice here, except to make |> > most of your cores interruptible. >> |> |> Async presumes processors are a scarce commodity and you want to >> have it >> |> do other work while it's waiting for something to be done. That goes >> |> away if you have unlimited numbers of processors. >> >> Not really. Let's assume that you do have such an infinite number of >> threads, and thread A wants to prod thread B at a time it is doing >> something >> else. That can't be done without some form of asynchronicity. > > Why would B be doing something else if you have an infinite number of > threads > on hand to do that something else? Because the 'something else' that Thread B is doing is the reason that Thread A needs to communicate with it. Duh. It is of course possible to program all threads such that they frequently poll some shared (and appropriately interlocked) portion of RAM to see whether anyone has left a message there for them, but that's equally possible with today's SMPs and doesn't seem to be the mechanism of choice a lot of the time. - bill
From: Chris Thomasson on 28 Sep 2006 21:49 "Joe Seigh" <jseigh_01(a)xemaps.com> wrote in message news:e7KdnXEkRJml04HYnZ2dnUVZ_tydnZ2d(a)comcast.com... > Terje Mathisen wrote: >> Joe Seigh wrote: >> >>> Terje Mathisen wrote: > Maybe. There's things like bus snooping which doesn't contribute to > memory usage. It doesn't matter. The IPC mechanism might end up looking > totally different than anything we know today. The processors > manufacturers > will have to solve it by the time they get up 100's of cores. Why not PDR on the hardware: http://groups.google.com/group/comp.programming.threads/msg/6236a9029d80527a I mentioned this idea of mine to Andy Glew: http://groups.google.com/group/comp.arch/msg/2a0f4163f8e13f1e I have not received any sort of response... Andy, are you there? ;) Any thoughts' on my PDR w/ hardware assist design? My idea can scale to any number of processors. Lock-free reader patterns can scale. Period.
From: Joe Seigh on 28 Sep 2006 22:30 Chris Thomasson wrote: > "Joe Seigh" <jseigh_01(a)xemaps.com> wrote in message > news:e7KdnXEkRJml04HYnZ2dnUVZ_tydnZ2d(a)comcast.com... > >>Terje Mathisen wrote: >> >>>Joe Seigh wrote: >>> >>> >>>>Terje Mathisen wrote: > > >>Maybe. There's things like bus snooping which doesn't contribute to >>memory usage. It doesn't matter. The IPC mechanism might end up looking >>totally different than anything we know today. The processors >>manufacturers >>will have to solve it by the time they get up 100's of cores. > > > Why not PDR on the hardware: > > http://groups.google.com/group/comp.programming.threads/msg/6236a9029d80527a > > I mentioned this idea of mine to Andy Glew: > > http://groups.google.com/group/comp.arch/msg/2a0f4163f8e13f1e > > I have not received any sort of response... Andy, are you there? > > ;) > > > Any thoughts' on my PDR w/ hardware assist design? My idea can scale to any > number of processors. Lock-free reader patterns can scale. Period. > > I don't know. I haven't event seen McKenney file any hardware patents in that area and he would have been the likely one to do that kind of stuff. The IPC would be more than just PDR. The whole memory model could change and they go to something like Occam style message passing. Because I don't think the current strongly coherent cache scheme will scale up. Of course that PDR supports a more relaxed cache/memory model doesn't hurt things. -- Joe Seigh When you get lemons, you make lemonade. When you get hardware, you make software.
From: Nick Maclaren on 29 Sep 2006 04:23
In article <451c19e0$1(a)darkstar>, eugene(a)cse.ucsc.edu (Eugene Miya) writes: |> In article <efgr7e$6oa$1(a)gemini.csx.cam.ac.uk>, |> Nick Maclaren <nmm1(a)cus.cam.ac.uk> wrote: |> >|> PIMs. |> > |> >When are we going to see them, then? |> |> We? "What do you mean 'we?' white man?" --Tonto |> I've seen them. I'm under an NDA. Well, actually, many people have. The ICL DAP (and, I believe, the BBN Butterfly) could well be classified as prototypes. The issue is when (and if!) they will be available openly enough and cheaply enough for a wide range of people to experiment with. And 20+ years from being the next great thing to mere NDA isn't exactly rapid progress .... |> >Seriously, they have been talked about as imminent for 20 years, so |> >either there is a major problem or the IT industry is suffering a |> >collective failure of nerve. Or both. |> |> You have to locate the knowledgeable in your country. Eh? Delivery is as delivery does. Damn the claims - let's see the products. Regards, Nick Maclaren. |