How Many Processor Cores Are Enough?
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From: Nick Maclaren on 29 Sep 2006 04:25 In article <451C39F9.3040708(a)ce.berkeley.edu>, Jon Forrest <forrest(a)ce.berkeley.edu> writes: |> |> If I remember correctly, in the early days of X, slow single |> processor systems with limited memory resulted in noticeable |> latencies for this reason. And, God help us, modern multi-core, multi-GB systems STILL show such delays even when there is almost no background activity :-( No matter how much power a desktop has, the bloatware specialists are fully capable of running out of it. Regards, Nick Maclaren.
From: kenney on 29 Sep 2006 07:15 In article <2KGdnWmuYvz-m4HYnZ2dnUVZ_tmdnZ2d(a)comcast.com>, jseigh_01(a)xemaps.com (Joe Seigh) wrote: > Ok, let me pose this question then. What are the limits to > how many cores one can imagine using? Are there fundimental > laws of logic here, or are we the next generation of punch card > mentality? Apart from any logical limit there are physical limits. First Chip fabs are limited in the size of wafer they can handle, Second there are packaging limits. All the cores are generating heat you have to get rid off. Also interconnection becomes a problem not just inside the package but from the package to it's socket. It took the abandonment of the dual in line package to give enough pins for modern processors. There are also limits on how much you can shrink the fab limits without needing a quantum physicist to design chips. Get things small enough and quantum tunnelling will become a major factor. I do not have enough information to make any predictions on what effect those limits will have on design. However I can see that a change in architecture might be appropriate. Possibly something on the lines of the old vector processors where most of the cores are just ALU with memory access being handled by a dedicated core. Or come to that revert to the transputer design an put multiple ones on the chip with a memory control unit to give parallel access to main memory. Ken Young
From: Joe Seigh on 29 Sep 2006 08:27 kenney(a)cix.compulink.co.uk wrote: > In article <2KGdnWmuYvz-m4HYnZ2dnUVZ_tmdnZ2d(a)comcast.com>, > jseigh_01(a)xemaps.com (Joe Seigh) wrote: > > >>Ok, let me pose this question then. What are the limits to >>how many cores one can imagine using? Are there fundimental >>laws of logic here, or are we the next generation of punch card >>mentality? > > > Apart from any logical limit there are physical limits. First > Chip fabs are limited in the size of wafer they can handle, > Second there are packaging limits. All the cores are generating > heat you have to get rid off. Also interconnection becomes a > problem not just inside the package but from the package to it's > socket. It took the abandonment of the dual in line package to > give enough pins for modern processors. There are also limits on > how much you can shrink the fab limits without needing a quantum > physicist to design chips. Get things small enough and quantum > tunnelling will become a major factor. > > I do not have enough information to make any predictions on what > effect those limits will have on design. However I can see that a > change in architecture might be appropriate. Possibly something > on the lines of the old vector processors where most of the cores > are just ALU with memory access being handled by a dedicated > core. Or come to that revert to the transputer design an put > multiple ones on the chip with a memory control unit to give > parallel access to main memory. > I don't disagree with you. Those are all valid points. But you are arguing the premise. So maybe I'll withdraw the question at this point. From a software perspective, there isn't much you can do to influence what hardware vendors will do. There's no such thing as too many cores or not enough cores. There is just whatever there is and you can either use it or not. I find the proclamations from Intel and such that software programmers, as a group, need to learn how to parallelize programs better rather amusing. We, as a group, don't need to do anything. It's Intel's problem. -- Joe Seigh When you get lemons, you make lemonade. When you get hardware, you make software.
From: Jon Forrest on 29 Sep 2006 14:07 Andi Kleen wrote: > Just because today's desktop software is mostly single threaded this doesn't mean > that future software has to be. Being multi-threaded is a start, but how many threads will be in runnable state simultaneously is what I'm wondering about (for general purpose computing). Jon
From: Thomas Womack on 29 Sep 2006 14:11
In article <7IKdnUrZObRC_4HYnZ2dnUVZ_oKdnZ2d(a)metrocastcablevision.com>, Bill Todd <billtodd(a)metrocast.net> wrote: >Tommy Thorn wrote: >> Bill Todd wrote: >>> Well, since IIRC the processing cores are running at a princely 1.91 MHz >> >> Well, you recall incorrectly. It's 3 GHz, cf. >> http://www.tomshardware.com/2006/09/27/idf_fall_2006/page2.html > >You really need to work on your reading comprehension: there is nothing >on the page that you cite above that remotely suggests that the >prototype runs at 3 GHz (the only mention of that clock rate is in >reference to a current P4's FP performance). Go to the source http://www.intel.com/pressroom/kits/events/idffall_2006/pdf/IDF%2009-26-06%20Justin%20Rattner%20Keynote%20Transcript.pdf includes the paragraph 'We just got the silicon back earlier this week of our Terascale Research prototype. And as you can see in the accompanying diagram, each one of the 80 cores on this die consists of a simple processor. It has a simple instruction set -- not IA compatible; it's just has a simple instruction set that lets us do simple computations in floating point and basically push data across the on-die fabric that connects the 80-cores on this die together. Now, in aggregate, those 80 cores produce one teraflop of computing performance, so a single one of these Terascale Research prototypes is a one teraflop-class processor. It delivers an energy efficiency of 10 gigaflops per watt at its nominal operating frequency of 3.1 gigahertz. That's an order of magnitude better than anything available today.' and 'For each core on that die, there's a 256-kilobyte static RAM, and the aggregate bandwidth between all of the cores and all of those SRAM arrays is one trillion bytes per second, truly an astonishing amount of memory bandwidth.' >The reference that gives the 1.91 MHz figure is >http://www.theinquirer.net/default.aspx?article=34623 That's talking about a completely different project; if nothing else, it's explicitly described as IA-compatible (and is running WinXP), whilst the terascale chip is explicitly described as not. Tom |