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From: -jg on 11 Mar 2010 17:22
On Mar 12, 9:19 am, Tier Logic <jeff.ka...(a)gmail.com> wrote:
> All I can tell you is come get a quote and we can save you money.
> Xilinx and Altera love all the skepticism here and want you to
> conitnue paying too much for your solutions.
So you have real, shipping silicon ? Great!
You claim 'we can save you money', Great too!!
- I love a clairvoyant supplier, who knows already
what packages and prices points I have!!.
- now tell me what packages, speeds and logic counts
you offer, as before I can _actually_ 'save money' here in the real
world, first the product actually has to be functional in a circuit
board that I can sell !!
From: -jg on 11 Mar 2010 17:25
On Mar 12, 10:31 am, whygee <y...(a)yg.yg> wrote:
> I'll take the example of a competitor.
> SiliconBlue has maybe "slow" chips
> (according to only one test I did)....
> The Actel ProAsic3 family is working very fine
> for me and wonder how it can be displaced.
We have ProASIC3 and SiliconBlue on a short list.
[maybe SmartFusion too, depends on $/package choices]
I'm interested in how much slower were the SiliconBlue devices ?
What tests did you do to compare them ?
From: whygee on 11 Mar 2010 17:31
> On Mar 12, 10:31 am, whygee <y...(a)yg.yg> wrote:
> We have ProASIC3 and SiliconBlue on a short list.
> [maybe SmartFusion too, depends on $/package choices]
wait a bit before things stabilize
and the distributors sing to the same tune.
I met Future and Actel France
today at the annual parisian Actel seminar,
I was not interested by their new offering,
I'm waiting for an eventual next generation with
a better SRAM/logic ratio.
> I'm interested in how much slower
> were the SiliconBlue devices ?
> What tests did you do to compare them ?
disclaimer : I'm not as good as Antti ;-)
HE has the boards and can tell more acurate
stories than mine.
I "only" installed their SW, and tried to
compile a simple adder design, probably
http://yasep.org/VHDL/asu_rop2/testdiff.vhd (test nr 1)
and got such a low MHz rating that I thought
that I hit the wrong button or something like that.
I tweaked many stuff and could not influence
the result much, tried different architectures...
and I gave up.
It just means that it did not meet my expectations.
I know that SBt's chips are created for ultraultralow power
and low speed. I'm not expecting Virtex performance
but i'm demanding anyway ;-)
If you want acurate figures, I prefer that you
try yourself, because i'm not sure why it is slow.
i've read "80MHz performance" or something like that
in the datasheets at the time
but like other FPGA claims, i'm not able to reach them.
I've seen people able to do about 300MHz designs
with ProASIC, I can only do 100MHz and Actel's
soft ARM maxes at around 60MHz... for a chip that
is meant to be "able of 350MHz".
so test yourself :-)
http://ygdes.com / http://yasep.org
From: Kim Enkovaara on 12 Mar 2010 01:14
> The claim of Auto-generate test vectors is interesting.
> Who pays for < 100% coverage 'issues' ?
When have you seen ASIC with 100% test coverage. It is either
impossible or the amount of vectors would be so huge that the
tester time would make the chip very expensive. Tester time
is quite big part of the chip price.
> merely stacked, so die size has shifted to more process steps. Raw
> silicon is actually quite cheap.
Wafers are not that cheap. Altough big part of the cost are the
process steps trough the fab.
> If your package is IO bound, then die size claims are
> totally illusory.
You can pack IOs also inside the die, not only to the boundaries.
IO bound vs. logic bound problems have diminished with some cell
From: Peter Alfke on 12 Mar 2010 14:33
From the official TIER website:
Tier Logic intends support to be a differentiator from the mainstream
FPGA vendors, who increasingly focus their support on only a few
select customers, ignoring or providing poor-quality support to all
but their largest accounts. Our approach is not to attempt to support
thousands of customers, but to sign up to deliver high-quality support
to every customer with whom we engage.
Please register to get full access to the Tier Logic website."
They hired a 13-year Altera veteran as VP of marketing and sales.
Where did he pick up such contorted writing and negative reasoning ?
It is unprofessional, to say the least.