From: rickman on
On Mar 11, 9:32 am, John_H <newsgr...(a)johnhandwork.com> wrote:
>
> I want better solutions to succeed.  *I* won't pursue vague promises
> but I'll consider real information.  Big difference.

I am also glad to hear from the Tier representative. I don't think of
discussing the technical issues of their product to be spamming, even
if it is from a "marketing" perspective.

As to the "vague" promises, the bottom line of what Tier is offering
is price... and we won't know that until we actually have a chance to
compare apples to apples. Heck, you can't even compare Xilinx and
Altera until you get them both in your office (tagging along with the
local disti) and get hard quotes. We all know how there is no such
thing as "list" price when it comes to used cars or FPGAs. In that
regard, Tier is no different than X or A or L or the other A.

Rick
From: rickman on
On Mar 11, 2:08 pm, -jg <jim.granvi...(a)gmail.com> wrote:
> On Mar 12, 3:32 am, John_H <newsgr...(a)johnhandwork.com> wrote:
>
> > > The TierASIC is tested with a scan-based ASIC methodology we added to
> > > the silicon. The customer is not required to generate any test
> > > vectors. Once you lock your design, you simply send us the bitstream
> > > and we auto generate the test vectors for your ASIC.
>
> The claim of Auto-generate test vectors is interesting.
> Who pays for < 100% coverage 'issues' ?
>
> > While I can understand the savings brought from removing the
> > configuration memories and associated die size, I still envision the
> > FPGA-like overhead as being significant since routing is such a large
> > portion of typical FPGA resources.  
>
>  The memory has not gone away, in the FPGA flow is it
> merely stacked, so die size has shifted to more process steps. Raw
> silicon is actually quite cheap.
>
>  Even in their ASIC flow, that 'memory ghost' remains, as the die size
> is locked to the larger of the two possible choices. Their fpga to
> asic step saving
> is some process steps, testing savings, and yield gains
> as they hope you are not using defects.
>
>  Where die size savings really kick in, is when they allow MORE logic
> into what is a 'practical size ceiling' - but we still have no
> indications of WHO their customers are ? - no logic or package info ?.
>
>  If your package is IO bound, then die size claims are
> totally illusory.
>
> -jg

Even if any given device size is IO bound, there is still a savings if
they are able to build the same capacity using an more mature and less
expensive processing technology. I seem to recall some number being
quoted on a process that is not near the 45 nm currently used in
FPGAs. I am sure their first devices won't be using the most
expensive processes.

Rick
From: rickman on
On Mar 12, 2:33 pm, Peter Alfke <al...(a)sbcglobal.net> wrote:
> From the official TIER website:
>
> "Support:
> Tier Logic intends support to be a differentiator from the mainstream
> FPGA vendors, who increasingly focus their support on only a few
> select customers, ignoring or providing poor-quality support to all
> but their largest accounts. Our approach is not to attempt to support
> thousands of customers, but to sign up to deliver high-quality support
> to every customer with whom we engage.
>
> Please register to get full access to the Tier Logic website."
>
> Peter says:
> They hired a 13-year Altera veteran as VP of marketing and sales.
> Where did he pick up such contorted writing and negative reasoning ?
> It is unprofessional, to say the least.

I hadn't seen that. I don't see this as "contorted", but rather very
well stated without raising alarms. It is saying, without being a
blunt instrument, that they are going to support all of their
customers, but they are going to be choosy about their customers.
They won't have thousands to support because they won't have thousands
of customers. That sounds like the course TI has always taken with
their automotive product lines, including their original ARM devices,
that you couldn't even get a data sheet on unless you could show you
would be buying millions. I ran into this wall with TI once.

Rick
From: rickman on
On Mar 11, 4:31 pm, whygee <y...(a)yg.yg> wrote:
> Hello,
>
> Tier Logic wrote:
> > All I can tell you is come get a quote and we can save you money.
>
> it is a curious statement !
> I assume that you have been too long in "stealth mode".
>
> Now I tell you this :
> "show me your public price list, your products,
> demo boards, detailed datasheet and distributors.
> Then maybe I'll choose you for a project".
>
> I'll take the example of a competitor.
> SiliconBlue has maybe "slow" chips
> (according to only one test I did) but they got
> it almost right for the rest, at least for me :
>   - decent development tool (not bloated)
>      that installs easily on Linux AND Windows !
>   - datasheet and other informations, enough to understand
>      how it is ticking inside so it can be used
>   - at least one distributor that talks to anyone
>      (even though the distributor is not large,
>       at least it does its job and doesn't scare potential customers)
>   - unit price that is decent is small quantities.
>   - ultra-low power is a plus but not critical for me.
>
> And still it's not functional enough for me.
> Antti has developped for it and I'm curious.
> Now before you can save me money, try to beat SBt,
> and then... beat the others :-P
> The Actel ProAsic3 family is working very fine
> for me and wonder how it can be displaced.
>
> good luck,

I'm curious, how many devices do you use in a year. I will bet if you
use less than 100k and possibly, 1 million, you won't get their
attention or even a quote.

Any takers?

Rick
From: John_H on
On Mar 12, 10:22 pm, rickman <gnu...(a)gmail.com> wrote:
>
> I'm curious, how many devices do you use in a year.  I will bet if you
> use less than 100k and possibly, 1 million, you won't get their
> attention or even a quote.
>
> Any takers?
>
> Rick

They quoted "free NRE" for a purchase commitment of $100k, I believe.
So if you want $100k worth of parts, I think they're already on board.

I just don't have a clue as to whether these are low cost and
performance devices, high performance and high density chips, or just
what they're shooting for. If they don't hit the aggressive
production nodes for the base layers (with a coarser layer 9 metal
mask process for a cheaper customization) then how can they truly
compete on the piece costs given the overhead for routing resources?

Whatever.