Tier Logic introduces the world's first 3D FPGA
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From: whygee on 14 Mar 2010 17:36 -jg wrote: > On Mar 15, 4:25 am, rickman <gnu...(a)gmail.com> wrote: >> The point is that using an older process (130 nm) Lattice is competing >> with products built on newer processes (90 nm Spartan 3A, et al). > > Yes, and your example shows a gap : As the FPGAs push higher in pin- > counts and packages, they leave a widening tail-end, where you need a > low-mfg-cost package, but a CPLD does not cut it. > > I believe there is another market opening, for a device that has more > ram, but not massive I/O counts. I see Actel and SiliconBlue trying to fill this market. It's interesting, I did not understand their effort in the beginning... And now that I have needs for exactly that (i'm trying to displace/replace my classic µC), they are welcome :-) > -jg yg -- http://ygdes.com / http://yasep.org
From: Brian Drummond on 14 Mar 2010 18:41 On Sun, 14 Mar 2010 08:27:06 -0700 (PDT), rickman <gnuarm(a)gmail.com> wrote: >On Mar 14, 9:04�am, whygee <y...(a)yg.yg> wrote: >> hi, >> >> I understand. >> I can't count the neighbours who asked me to repair their stuff... >> I keep repeating "I design, I don't repair others' stuff". >> >> good luck, > >Yeah, I also get people asking me about their house wiring! > >:^) A friend of mine, now retired, formerly involved in digital audio design at the BBC, was getting fed up of this at a party. So, on discovering the questioner was a marine biologist, he asked her about the best brand of fish fingers... (US: fish sticks) :-) - Brian
From: Jeff Cunningham on 14 Mar 2010 20:47 On 3/13/10 10:35 PM, rickman wrote: >> >> > 1 million, you won't get their attention or even a quote. >> I can get quotes from others, so why not from TierLogic ? > > I don't understand the question. The point is they can't make enough > money from a small user to make it worth their while. So they exclude > the engineers that won't make them much money and deal with the flak > from that rather than get a bad rep from not being able to support > every engineer with a wild hair. > > What part of this is hard to understand? I don't understand why selling to the small users and not supporting them well and therefore losing some sales from them because of "bad rep" would be a worse business strategy than imposing a boycott on yourself and not selling any parts at all to any of that group of people. Are you saying that the bad rep among the little guys would rub off onto even the big customers that do get good support? It seems kind of weird to me, but what do I know. Jeff
From: rickman on 15 Mar 2010 01:19 On Mar 14, 4:39 pm, -jg <jim.granvi...(a)gmail.com> wrote: > On Mar 15, 4:25 am, rickman <gnu...(a)gmail.com> wrote: > > > > > On Mar 14, 8:26 am, Uwe Bonnes <b...(a)elektron.ikp.physik.tu- > > > darmstadt.de> wrote: > > > rickman <gnu...(a)gmail.com> wrote: > > > > ... > > > > > As an example, show me a part from Xilinx or Altera that sells for > > > > under $10 in qty 100. I don't care what size, but an FPGA, not a > > > > CPLD. I am using the smallest part I can get (although I would like > > > > bigger, it just doesn't come in the 100 TQFP) and am paying under $10 > > > > making batches of 100-200 boards at a time. I couldn't find that > > > > price anywhere else but Lattice. > > > > The XC3S50A-4VQG100C sells for 5.52$ at Digikey > > > Ok, the way I made the statement I stand corrected. Someone else > > emailed me about Actel parts in this price range. But these parts > > have half the logic of the Lattice part. The Actel part in the same > > size range is half again as pricey and the Xilinx part in the same > > size range is about the same price, but lacking the config memory. > > That depends on where you set the threshold. > We have an app, that needs PLL+BlockRam, and not a huge > amount of logic. - same package dictates as yours. > > On this yardstick, Actel are now in front with the ProASCI3 at > $5.26/100+, but the smallest Lattice LFXP3C is $10.93/100+, the > Lattice LCMXO1200C is $11.50, whilst the XP2-5 is higher in price and > package. > Xilinx need Loader memory added to their OK price, > and the -3AN fails the package test. > > Actel also have to other choices, in the same package, at $7.23 and > $8.94, so have some upgrade elasticity. [Lattice show just the one > choice] > > > The point is that using an older process (130 nm) Lattice is competing > > with products built on newer processes (90 nm Spartan 3A, et al). > > Yes, and your example shows a gap : As the FPGAs push higher in pin- > counts and packages, they leave a widening tail-end, where you need a > low-mfg-cost package, but a CPLD does not cut it. > > I believe there is another market opening, for a device that has more > ram, but not massive I/O counts. I agree that there are opportunities at the low end. I don't know exactly what mix is optimal, but even the XP3C part I am using is an older technology for Lattice. If they make an XP2 in 100 pin part, the price would be lower than in the higher pin count packages and that is what I would be using. I need the gates! But as we have been discussing, there is little incentive for the FPGA makers to flesh out their low end parts. It just doesn't have the same profit margin or even total profit. At some point I am going to have to move to a larger pin count BGA package if I want a bigger LUT count. I've tried talking to the company reps until I am blue in the face, they ain't gonna support the low end like they do the top. Rick
From: whygee on 15 Mar 2010 02:30
rickman wrote: > I agree that there are opportunities at the low end. I don't know > exactly what mix is optimal, but even the XP3C part I am using is an > older technology for Lattice. If they make an XP2 in 100 pin part, > the price would be lower than in the higher pin count packages and > that is what I would be using. I need the gates! similar problem with Actel, I was explained that the large die size can't fit in smaller packages than what is proposed... too bad :-/ > Rick yg -- http://ygdes.com / http://yasep.org |